diff options
Diffstat (limited to 'hdl/core/reg.py')
| -rw-r--r-- | hdl/core/reg.py | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/hdl/core/reg.py b/hdl/core/reg.py index 0fee155..3526408 100644 --- a/hdl/core/reg.py +++ b/hdl/core/reg.py @@ -3,9 +3,9 @@ from amaranth import * from amaranth.sim import Settle from hdl.lib.in_out_buff import InOutBuff -from hdl.utils import cmd, step, sim +from hdl.utils import * -from hdl.core.alu import ALUFlags, ALU +from hdl.core.alu import ALUFlags @unique @@ -32,7 +32,7 @@ class Reg(Elaboratable): self.rs1_addr = Signal(4) self.rs2_addr = Signal(4) - self.alu_flgs = Signal(ALU().alu_flags.width) # flags from alu + self.alu_flgs = Signal(len(ALUFlags)) # flags from alu # these signals should be used one hot only self.int_sig = Signal(1) # unconditional interrupt |