diff options
Diffstat (limited to 'hdl/core/alu.py')
| -rw-r--r-- | hdl/core/alu.py | 58 |
1 files changed, 26 insertions, 32 deletions
diff --git a/hdl/core/alu.py b/hdl/core/alu.py index 789c26e..4380b8e 100644 --- a/hdl/core/alu.py +++ b/hdl/core/alu.py @@ -2,7 +2,7 @@ from amaranth import * from amaranth.sim import Simulator, Settle, Delay from enum import Enum, unique -from hdl.utils import * +from hdl.utils import sim, e2s, cmd, rand_bits_mix from hdl.lib.in_out_buff import InOutBuff from hdl.config import NUM_RAND_TESTS @@ -49,7 +49,7 @@ class ALU(Elaboratable): self.alu_flags = Signal(len(ALUFlags), reset_less=True) # alu flags is one hot self.out = Signal(32, reset_less=True) - self.sim = kargs["sim"] if "sim" in kargs else None + self.sim = kargs.get('sim', False) ports_in = [self.in1, self.in2, self.op, self.c_in] ports_out = [self.c_in, self.out, self.alu_flags] @@ -58,11 +58,6 @@ class ALU(Elaboratable): def elaborate(self, platform=None): m = Module() - # dummy sync for simulation only - if self.sim == True: - dummy = Signal() - m.d.sync += dummy.eq(~dummy) - with m.Switch(self.op): with m.Case(AluOpCodes.add.value): m.d.comb += self.tmp.eq(self.in1 + self.in2) @@ -142,7 +137,6 @@ def sub_proc(dut, val1, val2, c_in=0): yield dut.in1.eq(val1) yield dut.in2.eq(val2) yield dut.c_in.eq(c_in) - yield yield Settle() # test addition @@ -153,7 +147,7 @@ def test_alu_add(): yield from sub_proc(dut, 27, 13) out = yield dut.out assert 27 + 13 == (out), f'ERROR: {out} != {27 + 13}' - sim(dut, proc) + sim(dut, proc, sync=False) # test addition with carry def test_alu_addc(): @@ -163,7 +157,7 @@ def test_alu_addc(): yield from sub_proc(dut, 11, 43, 1) out = yield dut.out.as_signed() assert 11 + 43 + 1 == out, f'ERROR: {out} != {11 + 43 + 1}' - sim(dut, proc) + sim(dut, proc, sync=False) # test subtraction def test_alu_sub(): @@ -173,7 +167,7 @@ def test_alu_sub(): yield from sub_proc(dut, 25, 13) out = yield dut.out assert 25 - 13 == out, f'ERROR: {out} != {25 - 13}' - sim(dut, proc) + sim(dut, proc, sync=False) # test subtraction with carry def test_alu_subc_0(): @@ -183,7 +177,7 @@ def test_alu_subc_0(): yield from sub_proc(dut, 25, -13, 0) out = yield dut.out.as_signed() assert 25 + 13 -1 +0 == out, f'ERROR: {out} != {25 + 13 -1 +0}' - sim(dut, proc) + sim(dut, proc, sync=False) # test subtraction with carry def test_alu_subc_1(): @@ -193,7 +187,7 @@ def test_alu_subc_1(): yield from sub_proc(dut, 25, -13, 1) out = yield dut.out.as_signed() assert 25 + 13 -1 +1 == out, f'ERROR: {out} != {25 + 13 -1 +1}' - sim(dut, proc) + sim(dut, proc, sync=False) # test binary and def test_alu_and(): @@ -203,7 +197,7 @@ def test_alu_and(): yield from sub_proc(dut, 0b10101011, 0b01010101) out = yield dut.out assert 0b00000001 == out, f'ERROR: {out} != {0b00000001}' - sim(dut, proc) + sim(dut, proc, sync=False) # test binary or def test_alu_or(): @@ -213,7 +207,7 @@ def test_alu_or(): yield from sub_proc(dut, 0b10101011, 0b01000101) out = yield dut.out assert 0b11101111 == out, f'ERROR: {out} != {0b11101111}' - sim(dut, proc) + sim(dut, proc, sync=False) # test binary nor def test_alu_nor(): @@ -223,7 +217,7 @@ def test_alu_nor(): yield from sub_proc(dut, 0b10001011, 0b01000101) out = yield dut.out assert 0b11111111111111111111111100110000 == out, f'ERROR: {bin(out)} != {bin(0b11111111111111111111111100110000)}' - sim(dut, proc) + sim(dut, proc, sync=False) # test binary xor def test_alu_xor(): @@ -233,7 +227,7 @@ def test_alu_xor(): yield from sub_proc(dut, 0b10001011, 0b01000101) out = yield dut.out assert 0b11001110 == out, f'ERROR: {out} != {0b11001110}' - sim(dut, proc) + sim(dut, proc, sync=False) # test logical shift left def test_alu_logic_shift_left(): @@ -245,7 +239,7 @@ def test_alu_logic_shift_left(): assert 0b00010110000000000000000000000000 == out, f'ERROR: {bin(out)} != {bin(0b00010110000000000000000000000000)}' out = yield dut.c_out assert 1 == out, f'ERROR: {out} != {1}' - sim(dut, proc) + sim(dut, proc, sync=False) # test logical shift right def test_alu_logic_shift_right(): @@ -257,7 +251,7 @@ def test_alu_logic_shift_right(): assert 0b1000 == out, f'ERROR: {bin(out)} != {bin(0b1000)}' out = yield dut.c_out assert 1 == out, f'ERROR: {out} != {1}' - sim(dut, proc) + sim(dut, proc, sync=False) # test arithmetic shift right def test_alu_arith_shift_right(): @@ -269,7 +263,7 @@ def test_alu_arith_shift_right(): assert 0xF8000123 == out, f'ERROR: {out} != {0xF8000123}' out = yield dut.c_out assert 0 == out, f'ERROR: {out} != {0}' - sim(dut, proc) + sim(dut, proc, sync=False) # test low unsigned multiply def test_alu_mul_low_u(tests=NUM_RAND_TESTS): @@ -283,11 +277,11 @@ def test_alu_mul_low_u(tests=NUM_RAND_TESTS): in2 = rand_bits_mix(32, sus='u') yield dut.in1.eq(in1) yield dut.in2.eq(in2) - yield from eval() + yield Settle() expected = (in1 * in2) & 0xFFFFFFFF assert (yield dut.out) == expected, f"mul_low_u failed: in1={hex(in1)}, in2={hex(in2)}, out={hex((yield dut.out))}, expected={hex(expected)}" - sim(dut, proc) + sim(dut, proc, sync=False) # test high unsigned multiply def test_alu_mul_high_u(tests=NUM_RAND_TESTS): @@ -301,11 +295,11 @@ def test_alu_mul_high_u(tests=NUM_RAND_TESTS): in2 = rand_bits_mix(32, sus='u') yield dut.in1.eq(in1) yield dut.in2.eq(in2) - yield from eval() + yield Settle() expected = ((in1 * in2) >> 32) & 0xFFFFFFFF assert (yield dut.out) == expected, f"mul_high_u failed: in1={hex(in1)}, in2={hex(in2)}, out={hex((yield dut.out))}, expected={hex(expected)}" - sim(dut, proc) + sim(dut, proc, sync=False) # test low signed multiply def test_alu_mul_low_s(tests=NUM_RAND_TESTS): @@ -319,11 +313,11 @@ def test_alu_mul_low_s(tests=NUM_RAND_TESTS): in2 = rand_bits_mix(32, sus='s') yield dut.in1.eq(in1) yield dut.in2.eq(in2) - yield from eval() + yield Settle() expected = (in1 * in2) & 0xFFFFFFFF assert (yield dut.out) == expected, f"mul_low_s failed: in1={hex(in1)}, in2={hex(in2)}, out={hex((yield dut.out))}, expected={hex(expected)}" - sim(dut, proc) + sim(dut, proc, sync=False) # test high signed multiply def test_alu_mul_high_s(tests=NUM_RAND_TESTS): @@ -337,11 +331,11 @@ def test_alu_mul_high_s(tests=NUM_RAND_TESTS): in2 = rand_bits_mix(32, sus='s') yield dut.in1.eq(in1) yield dut.in2.eq(in2) - yield from eval() + yield Settle() expected = ((in1 * in2) >> 32) & 0xFFFFFFFF assert (yield dut.out) == expected, f"mul_high_s failed: in1={hex(in1)}, in2={hex(in2)}, out={hex((yield dut.out))}, expected={hex(expected)}" - sim(dut, proc) + sim(dut, proc, sync=False) # test unsigned overflow @@ -354,7 +348,7 @@ def test_alu_unsigned_overflow(): assert out == 1, f'ERROR: {out} != {1}' out = yield dut.c_out assert out == 1, f'ERROR: {out} != {1}' - sim(dut, proc) + sim(dut, proc, sync=False) # test unsigned underflow def test_alu_unsigned_underflow(): @@ -366,7 +360,7 @@ def test_alu_unsigned_underflow(): assert out == 1, f'ERROR: {out} != {1}' out = yield dut.c_out assert out == 0, f'ERROR: {out} != {0}' - sim(dut, proc) + sim(dut, proc, sync=False) # test zero def test_alu_zero_0(): @@ -376,7 +370,7 @@ def test_alu_zero_0(): yield from sub_proc(dut, 0, 1) # add 0 to 0 out = yield dut.zero assert out == 0, f'ERROR: {out} != {0}' - sim(dut, proc) + sim(dut, proc, sync=False) # test zero def test_alu_zero_1(): @@ -386,7 +380,7 @@ def test_alu_zero_1(): yield from sub_proc(dut, 0, 0) # add 0 to 0 out = yield dut.zero assert out == 1, f'ERROR: {out} != {1}' - sim(dut, proc) + sim(dut, proc, sync=False) |