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-rw-r--r--archive/myhdl/Makefile13
1 files changed, 13 insertions, 0 deletions
diff --git a/archive/myhdl/Makefile b/archive/myhdl/Makefile
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--- /dev/null
+++ b/archive/myhdl/Makefile
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+
+HDL_FOLDER = ./hdl
+HDL = $(wildcard $(HDL_FOLDER)/*.py)
+
+
+test:
+ py.test --disable-pytest-warnings -v $(HDL)
+
+test-w:
+ py.test -v $(HDL)
+
+clean:
+ $(RM) -rf simulation/* gen_verilog/* hdl/__pycache__ .pytest_cache \ No newline at end of file