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-rw-r--r--.vscode/configurationCache.log2
-rw-r--r--.vscode/dryrun.log5
-rw-r--r--.vscode/targets.log130
-rw-r--r--Makefile21
-rw-r--r--hdl/shift_reg.py (renamed from hdl/testing/shift_reg.py)32
-rw-r--r--hdl/testing/async_reset.py21
-rw-r--r--hdl/testing/multi_clock.py75
-rw-r--r--hdl/testing/v0
-rw-r--r--hdl/utils.py22
9 files changed, 241 insertions, 67 deletions
diff --git a/.vscode/configurationCache.log b/.vscode/configurationCache.log
index bab9054..7272748 100644
--- a/.vscode/configurationCache.log
+++ b/.vscode/configurationCache.log
@@ -1 +1 @@
-{"buildTargets":[],"launchTargets":[],"customConfigurationProvider":{"workspaceBrowse":{"browsePath":[],"compilerArgs":[]},"fileIndex":[]}} \ No newline at end of file
+{"buildTargets":["cc","clean","test","test-w"],"launchTargets":[],"customConfigurationProvider":{"workspaceBrowse":{"browsePath":[],"compilerArgs":[]},"fileIndex":[]}} \ No newline at end of file
diff --git a/.vscode/dryrun.log b/.vscode/dryrun.log
index e3eafb1..3712119 100644
--- a/.vscode/dryrun.log
+++ b/.vscode/dryrun.log
@@ -1,6 +1,5 @@
-make --dry-run --always-make --keep-going --print-directory
+make --dry-run --keep-going --print-directory
make: Entering directory '/home/jon/github/ASAP32'
+python3 hdl/shift_reg.py cc hdl/shift_reg
make: Leaving directory '/home/jon/github/ASAP32'
-make: *** No targets specified and no makefile found. Stop.
-
diff --git a/.vscode/targets.log b/.vscode/targets.log
index 5f84ce2..29b4ebe 100644
--- a/.vscode/targets.log
+++ b/.vscode/targets.log
@@ -1,4 +1,6 @@
make all --print-data-base --no-builtin-variables --no-builtin-rules --question
+make: *** No rule to make target 'all'. Stop.
+
# GNU Make 4.3
# Built for x86_64-suse-linux-gnu
# Copyright (C) 1988-2020 Free Software Foundation, Inc.
@@ -6,14 +8,18 @@ make all --print-data-base --no-builtin-variables --no-builtin-rules --question
# This is free software: you are free to change and redistribute it.
# There is NO WARRANTY, to the extent permitted by law.
-# Make data base, printed on Thu Aug 4 22:49:23 2022
+# Make data base, printed on Wed Aug 10 22:11:46 2022
# Variables
# environment
+PROVIDE_FULLSTACK_ACTION = true
+# environment
JAVA_HOME = /usr/lib64/jvm/java
# environment
QEMU_AUDIO_DRV = pa
+# makefile (from 'Makefile', line 2)
+HDL_FOLDER = ./hdl
# environment
GDK_BACKEND = x11
# environment
@@ -23,15 +29,19 @@ NO_AT_BRIDGE = 1
# environment
GTK_RC_FILES = /etc/gtk/gtkrc:/home/jon/.gtkrc:/home/jon/.config/gtkrc
# environment
+UUID = 30e4f429-d9ff-4340-ac46-25a56c8ba58c
+# environment
WINDOWMANAGER = /usr/bin/startplasma-x11
# environment
-VSCODE_CWD = /home/jon/github
+VSCODE_CWD = /home/jon
# environment
GPG_TTY = not a tty
# environment
MACHTYPE = x86_64-suse-linux
# default
MAKE_COMMAND := make
+# environment
+THREE_SCALE_USER_TOKEN = 207c527cfc2a6b8dcf4fa43ad7a976da
# automatic
@D = $(patsubst %/,%,$(dir $@))
# environment
@@ -63,7 +73,7 @@ XDG_DATA_DIRS = /home/jon/.local/share/flatpak/exports/share:/var/lib/flatpak/ex
# environment
QML_XHR_ALLOW_FILE_READ = 1
# environment
-VSCODE_CODE_CACHE_PATH = /home/jon/.config/Code/CachedData/3b889b090b5ad5793f524b5d1d39fda662b96a2a
+VSCODE_CODE_CACHE_PATH = /home/jon/.config/Code/CachedData/da76f93349a72022ca4670c1b84860304616aaa2
# environment
XDG_SESSION_PATH = /org/freedesktop/DisplayManager/Session0
# environment
@@ -73,7 +83,7 @@ SSH_ASKPASS = /usr/libexec/ssh/ssh-askpass
# environment
LANG = C
# environment
-XAUTHORITY = /run/user/1000/xauth_jFUnMm
+XAUTHORITY = /run/user/1000/xauth_xKCqdm
# environment
MANPATHISSET = yes
# default
@@ -87,6 +97,8 @@ MAKEFLAGS = pqrR
# makefile
CURDIR := /home/jon/github/ASAP32
# environment
+UTM_SOURCE = vscode
+# environment
APPLICATION_INSIGHTS_NO_DIAGNOSTIC_CHANNEL = 1
# environment
LESSOPEN = lessopen.sh %s
@@ -95,7 +107,7 @@ LESSOPEN = lessopen.sh %s
# environment
MFLAGS = -pqrR
# environment
-SSH_AUTH_SOCK = /tmp/ssh-XXXXXX6Sy2Am/agent.1730
+SSH_AUTH_SOCK = /tmp/ssh-XXXXXX5VtrVN/agent.1680
# default
.SHELLFLAGS := -c
# environment
@@ -110,12 +122,12 @@ XCURSOR_THEME = Qogir-dark
LESSKEY = /usr/etc/lesskey.bin
# environment
XDG_SESSION_DESKTOP = KDE
-# makefile
-MAKEFILE_LIST :=
+# makefile (from 'Makefile', line 1)
+MAKEFILE_LIST := Makefile
# automatic
@F = $(notdir $@)
# environment
-VSCODE_PID = 4695
+VSCODE_PID = 20613
# environment
XDG_SESSION_TYPE = x11
# environment
@@ -127,7 +139,7 @@ INPUT_METHOD = ibus
# environment
SDK_HOME = /usr/lib64/jvm/java
# environment
-SESSION_MANAGER = local/WarpDrive:@/tmp/.ICE-unix/2082,unix/WarpDrive:/tmp/.ICE-unix/2082
+SESSION_MANAGER = local/WarpDrive:@/tmp/.ICE-unix/2057,unix/WarpDrive:/tmp/.ICE-unix/2057
# automatic
*F = $(notdir $*)
# environment
@@ -135,7 +147,7 @@ MANPATH = /home/jon/.local/share/man:/usr/local/man:/usr/local/share/man:/usr/sh
# environment
CHROME_DESKTOP = code-url-handler.desktop
# environment
-DBUS_SESSION_BUS_ADDRESS = unix:abstract=/tmp/dbus-ymHqyeMEWm,guid=17b1d60c93f024c3f95adad862e5d7e3
+DBUS_SESSION_BUS_ADDRESS = unix:abstract=/tmp/dbus-E50q4J8Dmj,guid=72916cd557b4aa5740f764f362f2a65e
# automatic
<D = $(patsubst %/,%,$(dir $<))
# environment
@@ -179,6 +191,8 @@ MINICOM = -c on
# environment
CPU = x86_64
# environment
+RECOMMENDER_API_URL = https://gw.api.openshift.io//api/v2
+# environment
LESSCLOSE = lessclose.sh %s %s
# automatic
?F = $(notdir $?)
@@ -221,11 +235,11 @@ AUDIODRIVER = pulseaudio
# environment
G_FILENAME_ENCODING = @locale,UTF-8,ISO-8859-15,CP1252
# environment
-PLATFORMIO_PATH = /home/jon/.platformio/python3/bin:/home/jon/.local/bin:/usr/local/bin:/usr/bin:/bin:/opt/cross/bin
+PLATFORMIO_PATH = /home/jon/.platformio/penv/bin:/home/jon/.platformio/penv:/home/jon/.platformio/python3/bin:/home/jon/.local/bin:/usr/local/bin:/usr/bin:/bin:/opt/cross/bin
# environment
XDG_VTNR = 7
# makefile
-.DEFAULT_GOAL :=
+.DEFAULT_GOAL := cc
# environment
DISPLAY = :0
# environment
@@ -237,7 +251,7 @@ MAKE_VERSION := 4.3
# environment
KDE_SESSION_UID = 1000
# environment
-SSH_AGENT_PID = 1894
+SSH_AGENT_PID = 1790
# environment
PAGER = less
# environment
@@ -246,6 +260,10 @@ _ = /usr/bin/make
XDG_RUNTIME_DIR = /run/user/1000
# environment
G_BROKEN_FILENAMES = 1
+# makefile (from 'Makefile', line 3)
+HDL = $(wildcard $(HDL_FOLDER)/*.py)
+# environment
+GOLANG_EXECUTABLE = go
# environment
XDG_SESSION_CLASS = user
# environment
@@ -267,7 +285,7 @@ JDK_HOME = /usr/lib64/jvm/java
# environment
ELECTRON_RUN_AS_NODE = 1
# environment
-VSCODE_IPC_HOOK = /run/user/1000/vscode-74f3b1db-1.69.2-main.sock
+VSCODE_IPC_HOOK = /run/user/1000/vscode-74f3b1db-1.70.0-main.sock
# environment
TERM = xterm
# environment
@@ -285,6 +303,8 @@ SUFFIXES :=
# environment
QT_AUTO_SCREEN_SCALE_FACTOR = 0
# environment
+TELEMETRY_ID = b829c4ad-e5b7-4d5d-8ec4-ffd388ea5201
+# environment
LS_OPTIONS = -N --color=tty -T 0
# environment
KDE_SESSION_VERSION = 5
@@ -293,14 +313,12 @@ KDE_SESSION_VERSION = 5
# environment
QT4_IM_MODULE = xim
# environment
+
KDE_FULL_SESSION = true
# environment
-
-make: *** No rule to make target 'all'. Stop.
-
JRE_HOME = /usr/lib64/jvm/java
# variable set hash-table stats:
-# Load=143/1024=14%, Rehash=0, Collisions=13/170=8%
+# Load=152/1024=15%, Rehash=0, Collisions=19/186=10%
# Pattern-specific Variable Values
@@ -308,9 +326,10 @@ JRE_HOME = /usr/lib64/jvm/java
# Directories
-# . (device 65025, inode 21757987): 10 files, no impossibilities.
+# ./hdl (device 65025, inode 22952540): 8 files, no impossibilities.
+# . (device 65025, inode 21757987): 12 files, no impossibilities.
-# 10 files, no impossibilities in 1 directories.
+# 20 files, no impossibilities in 2 directories.
# Implicit Rules
@@ -318,12 +337,39 @@ JRE_HOME = /usr/lib64/jvm/java
# Files
+test-w:
+# Implicit rule search has not been done.
+# Modification time never checked.
+# File has not been updated.
+# recipe to execute (from 'Makefile', line 15):
+ py.test -v $(HDL)
+
+v: hdl/shift_reg.py hdl/utils.py
+# Implicit rule search has not been done.
+# Modification time never checked.
+# File has not been updated.
+# recipe to execute (from 'Makefile', line 9):
+ python3 $< v $(basename $< .py)
+
+# Not a target:
+hdl/shift_reg.py:
+# Implicit rule search has not been done.
+# Modification time never checked.
+# File has not been updated.
+
# Not a target:
Makefile:
# Implicit rule search has been done.
-# File does not exist.
+# Last modified 2022-08-10 22:11:10.968940293
# File has been updated.
-# Failed to be updated.
+# Successfully updated.
+
+clean:
+# Implicit rule search has not been done.
+# Modification time never checked.
+# File has not been updated.
+# recipe to execute (from 'Makefile', line 18):
+ $(RM) -rf $(HDL_FOLDER)/*.cc $(HDL_FOLDER)/*.v $(HDL_FOLDER)/*.vcd
# Not a target:
.DEFAULT:
@@ -339,33 +385,39 @@ all:
# File has not been updated.
# Not a target:
-makefile:
-# Implicit rule search has been done.
-# File does not exist.
-# File has been updated.
-# Failed to be updated.
+hdl/utils.py:
+# Implicit rule search has not been done.
+# Modification time never checked.
+# File has not been updated.
-# Not a target:
-GNUmakefile:
-# Implicit rule search has been done.
-# File does not exist.
-# File has been updated.
-# Failed to be updated.
+test:
+# Implicit rule search has not been done.
+# Modification time never checked.
+# File has not been updated.
+# recipe to execute (from 'Makefile', line 12):
+ py.test --disable-pytest-warnings -v $(HDL)
+
+cc: hdl/shift_reg.py hdl/utils.py
+# Implicit rule search has not been done.
+# Modification time never checked.
+# File has not been updated.
+# recipe to execute (from 'Makefile', line 6):
+ python3 $< cc $(basename $< .py)
# files hash-table stats:
-# Load=6/1024=1%, Rehash=0, Collisions=0/15=0%
+# Load=11/1024=1%, Rehash=0, Collisions=0/25=0%
# VPATH Search Paths
# No 'vpath' search paths.
# No general ('VPATH' variable) search path.
-# strcache buffers: 1 (0) / strings = 18 / storage = 147 B / avg = 8 B
-# current buf: size = 8162 B / used = 147 B / count = 18 / avg = 8 B
+# strcache buffers: 1 (0) / strings = 30 / storage = 261 B / avg = 8 B
+# current buf: size = 8162 B / used = 261 B / count = 30 / avg = 8 B
-# strcache performance: lookups = 21 / hit rate = 14%
+# strcache performance: lookups = 44 / hit rate = 31%
# hash-table stats:
-# Load=18/8192=0%, Rehash=0, Collisions=0/21=0%
-# Finished Make data base on Thu Aug 4 22:49:23 2022
+# Load=30/8192=0%, Rehash=0, Collisions=0/44=0%
+# Finished Make data base on Wed Aug 10 22:11:46 2022
diff --git a/Makefile b/Makefile
new file mode 100644
index 0000000..64ce203
--- /dev/null
+++ b/Makefile
@@ -0,0 +1,21 @@
+
+HDL_FOLDER = ./hdl
+HDL = $(wildcard $(HDL_FOLDER)/*.py)
+
+sim: $(HDL)
+ python3 $< sim
+
+cc: $(HDL)
+ python3 $< cc $(basename $< .py)
+
+v: $(HDL)
+ python3 $< v
+
+test:
+ py.test --disable-pytest-warnings -v $(HDL)
+
+test-w:
+ py.test -v $(HDL)
+
+clean:
+ $(RM) -rf $(HDL_FOLDER)/*.cc $(HDL_FOLDER)/*.v $(HDL_FOLDER)/*.vcd \ No newline at end of file
diff --git a/hdl/testing/shift_reg.py b/hdl/shift_reg.py
index b7c2290..dedc56b 100644
--- a/hdl/testing/shift_reg.py
+++ b/hdl/shift_reg.py
@@ -1,13 +1,16 @@
import sys
+from wsgiref.util import shift_path_info
from amaranth import *
from amaranth.back import verilog, cxxrtl
from amaranth.cli import main
from amaranth.sim import Simulator, Settle, Delay
-BASENAME = "shift_reg"
+from utils import cmd
class ShiftReg(Elaboratable):
def __init__(self, width):
+ self.name = "shift_reg"
+
self.load_val = Signal(width, reset=0, reset_less=True)
self.load = Signal()
self.reg = Signal(width)
@@ -30,12 +33,7 @@ class ShiftReg(Elaboratable):
return m
-
-def step():
- yield
- yield Settle()
-
-def test_shift_reg():
+def test_shift_reg(filename="out.vcd"):
dut = ShiftReg(8)
def proc1():
@@ -77,24 +75,10 @@ def test_shift_reg():
sim.add_clock(1e-6)
sim.add_sync_process(proc1)
- with sim.write_vcd(BASENAME + '.vcd'):
+ with sim.write_vcd(filename):
sim.run()
if __name__ == '__main__':
-
- if sys.argv[1] == "sim":
- test_shift_reg()
- exit()
-
- m = ShiftReg(8)
-
- if sys.argv[1] == "v":
- out = verilog.convert(m, ports=m.ports)
- with open(BASENAME + '.v','w') as f:
- f.write(out)
-
- elif sys.argv[1] == "cc":
- out = cxxrtl.convert(m, ports=m.ports)
- with open(BASENAME + '.cc','w') as f:
- f.write(out)
+ shift_reg = ShiftReg(8)
+ cmd(shift_reg, test_shift_reg) \ No newline at end of file
diff --git a/hdl/testing/async_reset.py b/hdl/testing/async_reset.py
new file mode 100644
index 0000000..4760df7
--- /dev/null
+++ b/hdl/testing/async_reset.py
@@ -0,0 +1,21 @@
+from amaranth import *
+from amaranth.cli import main
+
+
+class ClockDivisor(Elaboratable):
+ def __init__(self, factor):
+ self.v = Signal(factor)
+ self.o = Signal()
+
+ def elaborate(self, platform):
+ m = Module()
+ m.d.sync += self.v.eq(self.v + 1)
+ m.d.comb += self.o.eq(self.v[-1])
+ return m
+
+
+if __name__ == "__main__":
+ m = Module()
+ m.domains.sync = sync = ClockDomain("sync", async_reset=True)
+ m.submodules.ctr = ctr = ClockDivisor(factor=16)
+ main(m, ports=[ctr.o, sync.clk]) \ No newline at end of file
diff --git a/hdl/testing/multi_clock.py b/hdl/testing/multi_clock.py
new file mode 100644
index 0000000..e377156
--- /dev/null
+++ b/hdl/testing/multi_clock.py
@@ -0,0 +1,75 @@
+import sys
+from amaranth import *
+from amaranth.back import verilog, cxxrtl
+from amaranth.cli import main
+from amaranth.sim import Simulator, Settle, Delay
+
+BASENAME = "multi_clock"
+
+class SubM(Elaboratable):
+ def __init__(self, domain=None):
+ self.inv = Signal()
+ self.domain=domain
+
+ def elaborate(self, platform):
+ m = Module()
+
+ m.d.sync += self.inv.eq(~self.inv)
+
+ return m
+
+class top(Elaboratable):
+ def __init__(self):
+ self.sig_slow = Signal()
+ self.sig_fast = Signal()
+
+ self.div = Signal(2)
+
+ def elaborate(self, platform):
+ m = Module()
+
+ m.domains += ClockDomain('slow')
+ m.d.sync += [self.div.eq(self.div + 1)]
+ m.d.comb += ClockSignal('slow').eq(self.div[-1])
+
+ m.submodules.subm1 = SubM()
+ m.submodules.subm2 = DomainRenamer("slow")(SubM())
+
+ m.d.sync += self.sig_fast.eq(m.submodules.subm1.inv)
+ m.d.slow += self.sig_slow.eq(m.submodules.subm2.inv)
+
+ return m
+
+def test_shift_reg():
+ dut = top()
+
+ def proc1():
+ for _ in range(16):
+ yield
+ yield Settle()
+
+ sim = Simulator(dut)
+ sim.add_clock(1e-6)
+ sim.add_sync_process(proc1)
+
+ with sim.write_vcd(BASENAME + '.vcd'):
+ sim.run()
+
+
+if __name__ == '__main__':
+
+ if sys.argv[1] == "sim":
+ test_shift_reg()
+ exit()
+
+ # m = ShiftReg(8)
+
+ # if sys.argv[1] == "v":
+ # out = verilog.convert(m, ports=m.ports)
+ # with open(BASENAME + '.v','w') as f:
+ # f.write(out)
+
+ # elif sys.argv[1] == "cc":
+ # out = cxxrtl.convert(m, ports=m.ports)
+ # with open(BASENAME + '.cc','w') as f:
+ # f.write(out)
diff --git a/hdl/testing/v b/hdl/testing/v
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/hdl/testing/v
diff --git a/hdl/utils.py b/hdl/utils.py
new file mode 100644
index 0000000..6aad95f
--- /dev/null
+++ b/hdl/utils.py
@@ -0,0 +1,22 @@
+import sys
+from typing import Callable
+from amaranth import Elaboratable
+from amaranth.back import verilog, cxxrtl
+
+def cmd(hdl, tb:Callable):
+ if len(sys.argv) <= 1:
+ exit()
+
+ if sys.argv[1] == "sim":
+ tb(sys.argv[0].replace('.py', '.vcd'))
+ exit()
+
+ if sys.argv[1] == "v":
+ out = verilog.convert(hdl, ports=hdl.ports)
+ with open(sys.argv[0].replace('.py', '.v'), 'w') as f:
+ f.write(out)
+
+ elif sys.argv[1] == "cc":
+ out = cxxrtl.convert(hdl, ports=hdl.ports)
+ with open(sys.argv[0].replace('.py', '.cc'), 'w') as f:
+ f.write(out) \ No newline at end of file