diff options
| -rw-r--r-- | hdl/core/reg.py | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/hdl/core/reg.py b/hdl/core/reg.py index b6aa3c5..8dc1281 100644 --- a/hdl/core/reg.py +++ b/hdl/core/reg.py @@ -210,7 +210,8 @@ def test_reg_writeback_en(): assert (yield dut.zx) == 0, f'ERROR {dut.zx.name} != 0' elif i == dut.ip.idx: # ip should be incremented and not written to - assert (yield dut.reg_arr[i]) == i+1, f'ERROR {dut.ip.name} != {i + 1} should not be able to be directly written to' + print((yield dut.ip)) + assert (yield dut.reg_arr[i]) == dut.ip.idx+4, f'ERROR {dut.ip.name} != {dut.ip.idx+4} should not be able to be directly written to' sim(dut, proc) # check to make sure alu is writing values |