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authorjjsuperpower <jjs29356@gmail.com>2022-06-26 09:40:18 -0500
committerjjsuperpower <jjs29356@gmail.com>2022-06-26 09:40:18 -0500
commit987134966d0c3ab9b1a5775c8f01fa707408780b (patch)
tree47547791b41376ee25fd0968724d2e34a4742f60 /hdl_lab/myhdl_wrap.py
parentf4407898d3d74be98cdf1a0308c779cd842364ab (diff)
restructured folder
Diffstat (limited to 'hdl_lab/myhdl_wrap.py')
-rw-r--r--hdl_lab/myhdl_wrap.py31
1 files changed, 31 insertions, 0 deletions
diff --git a/hdl_lab/myhdl_wrap.py b/hdl_lab/myhdl_wrap.py
new file mode 100644
index 0000000..2e8fe4e
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+++ b/hdl_lab/myhdl_wrap.py
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+import os
+from myhdl import *
+from constants import *
+
+class Myhdl_Wrapper():
+ def __init__(self):
+ self.class_name = self.__class__.__name__
+
+ def _export(self, **kargs):
+ inst = getattr(self, self.class_name)(**kargs)
+ inst.convert(hdl='Verilog', path=GEN_VERILOG, name=f"{self.class_name}")
+
+
+
+ # This function links myhdl to icarus verilog sim
+ def _cosim(self, **kargs): #these should have the same signals as logic(),
+
+ iverilog_cmd = IVERILOG + f"-o {SIM_DIR}{self.class_name}.o {GEN_VERILOG}{self.class_name}.v {GEN_VERILOG}tb_{self.class_name}.v"
+ vvp_cmd = VVP + f"{SIM_DIR}{self.class_name}.o"
+
+ os.system(iverilog_cmd)
+ return Cosimulation(vvp_cmd, **kargs)
+
+ def sim(self):
+ tb = self.tb(getattr(self, self.class_name))
+ tb.config_sim(trace=True, tracebackup=False, directory=SIM_DIR, filename=f"{self.class_name}_sim")
+ tb.run_sim()
+
+ def cosim(self):
+ tb = self.tb(self._cosim)
+ tb.run_sim() \ No newline at end of file