summaryrefslogtreecommitdiff
path: root/hdl
diff options
context:
space:
mode:
authorjjsuperpower <jjs29356@gmail.com>2022-10-13 21:03:55 -0500
committerjjsuperpower <jjs29356@gmail.com>2022-10-13 21:03:55 -0500
commitbcb5a08e1ebd3e5ef5395bd6fd685c0ace7fa748 (patch)
treeeaa04b3b0700b01d3c59ce37b4ddd4afcabc13f2 /hdl
parent57576da32896277ee6010e314773290faf7ab561 (diff)
started on control
Diffstat (limited to 'hdl')
-rw-r--r--hdl/core/control.py64
1 files changed, 64 insertions, 0 deletions
diff --git a/hdl/core/control.py b/hdl/core/control.py
new file mode 100644
index 0000000..04efe74
--- /dev/null
+++ b/hdl/core/control.py
@@ -0,0 +1,64 @@
+from amaranth import *
+from amaranth.sim import Simulator, Settle, Delay
+from enum import Enum, unique
+
+from hdl.utils import *
+from hdl.lib.in_out_buff import InOutBuff # used for timing analysis
+
+from alu import AluOpCodes
+from jump_ctl import JumpOpCodes
+
+
+class Control(Elaboratable):
+ def __init__(self, **kargs):
+ self.instr_op = Signal(4, reset_less=True)
+
+ # out opcodes
+ self.alu_op = Signal(e2s(AluOpCodes))
+ self.jump_ctl_op = Signal(e2s(JumpOpCodes))
+
+ # register control out
+ self.wr_en = Signal(1)
+ self.stall = Signal(1)
+ self.int_sig = Signal(1)
+ self.iret = Signal(1)
+ self.call = Signal(1)
+ self.jump = Signal(1)
+
+ # register control in
+ self.int_en = Signal(1)
+ self.user_mode = Signal(1)
+
+ ports_in = [self.instr_op, self.alu_op, self.jump_ctl_op, self.wr_en, self.stall, self.int_sig, self.iret, self.call, self.jump]
+ ports_out = []
+ self.ports = {'in': ports_in, 'out': ports_out}
+
+ self.sim = kargs["sim"] if "sim" in kargs else False
+
+ def elaborate(self, platform=None):
+ m = Module()
+
+ # dummy sync for simulation only needed if there is no other sequential logic
+ if self.sim == True:
+ dummy = Signal()
+ m.d.sync += dummy.eq(~dummy)
+
+ ...
+
+ return m
+
+
+# test addition
+def test_hdl():
+ dut = Control(sim=True)
+ def proc():
+ yield from step #step clock
+ yield Settle() #needed if for combinatorial logic
+ yield dut.something #read value
+ sim(dut, proc)
+
+
+
+if __name__ == '__main__':
+ hdl = InOutBuff(Control())
+ cmd(hdl)