restructured folder

1 files changed, 0 insertions, 26 deletions

diff --git a/hdl/testing/top.py b/hdl/testing/top.py
deleted file mode 100644
index 72e14cd..0000000
--- a/hdl/testing/top.py
+++ /dev/null
@@ -1,26 +0,0 @@
-from myhdl import *
-from constants import GEN_VERILOG
-from shift_reg import ShiftReg
-
-logic = ShiftReg.ShiftReg
-
-@block
-def top(clk, reset, in0, out0):
-
-    node = Signal(modbv(0)[8:])
-
-    sr0 = logic(clk=clk, reset=reset, in0=in0, out0=node)
-    sr1 = logic(clk=clk, reset=reset, in0=node(7), out0=out0)
-
-    return sr0, sr1
-
-def convert():
-        reset = ResetSignal(0, 0, True)
-        clk = Signal(bool(0))
-        in0 = Signal(bool(0))
-        out0 = Signal(modbv(0)[8:])
-
-        inst = top(reset=reset, clk=clk, in0=in0, out0=out0)
-        inst.convert(hdl='Verilog', path=GEN_VERILOG)
-
-convert()
\ No newline at end of file