combine shiftreg working

1 files changed, 4 insertions, 6 deletions

diff --git a/hdl/testing/top.py b/hdl/testing/top.py
index 55c5714..72e14cd 100644
--- a/hdl/testing/top.py
+++ b/hdl/testing/top.py
@@ -2,17 +2,15 @@ from myhdl import *
 from constants import GEN_VERILOG
 from shift_reg import ShiftReg
 
-logic = ShiftReg.logic
-
+logic = ShiftReg.ShiftReg
 
 @block
 def top(clk, reset, in0, out0):
 
-    n0 = Signal(modbv(0)[8:])
-    
+    node = Signal(modbv(0)[8:])
 
-    sr0 = logic(clk=clk, reset=reset, in0=in0, out0=n0)
-    sr1 = logic(clk=clk, reset=reset, in0=n0[7], out0=out0)
+    sr0 = logic(clk=clk, reset=reset, in0=in0, out0=node)
+    sr1 = logic(clk=clk, reset=reset, in0=node(7), out0=out0)
 
     return sr0, sr1