reorganized hdl

1 files changed, 0 insertions, 80 deletions

diff --git a/hdl/shift_reg.py b/hdl/shift_reg.py
deleted file mode 100644
index 40af39b..0000000
--- a/hdl/shift_reg.py
+++ /dev/null
@@ -1,80 +0,0 @@
-from amaranth import *
-from amaranth.sim import Simulator, Settle, Delay
-
-from utils import cmd
-
-class ShiftReg(Elaboratable):
-    def __init__(self, width):
-        self.name = "shift_reg"
-
-        self.load_val = Signal(width, reset=0, reset_less=True)
-        self.load = Signal()
-        self.reg = Signal(width)
-        self.en = Signal()
-        self.right_left = Signal()
-
-        self.ports = [self.load_val, self.en, self.right_left, self.reg]
-
-    def elaborate(self, platform):
-        m = Module()
-
-        with m.If(self.load):
-            m.d.sync += self.reg.eq(self.load_val)
-        with m.Else():
-            with m.If(self.en):
-                with m.If(self.right_left):
-                    m.d.sync += self.reg.eq(self.reg << 1)
-                with m.Else():
-                    m.d.sync += self.reg.eq(self.reg >> 1)
-
-        return m
-
-def test_shift_reg(filename="out.vcd"):
-    dut = ShiftReg(8)
-
-    def proc1():
-        val = 0xAB
-
-        yield dut.load_val.eq(val)
-        yield dut.en.eq(0)
-        yield dut.load.eq(1)
-        yield
-        yield Settle()
-        yield dut.load.eq(0)
-        yield dut.en.eq(1)   
-
-        for _ in range(9):
-            reg_val = yield dut.reg
-            assert reg_val == val, f"Incorrect shift ---EXPECTED: {hex(val)}   ---GOT: {hex(reg_val)}"
-            val = val >> 1
-            yield
-            yield Settle()
-
-        val = 0xBD
-        yield dut.load_val.eq(val)
-        yield dut.load.eq(1)
-        yield dut.right_left.eq(1)
-        yield
-        yield Settle()
-        yield dut.load.eq(0)
-
-        for _ in range(9):
-            reg_val = yield dut.reg
-            assert reg_val == val, f"Incorrect shift ---EXPECTED: {hex(val)}   ---GOT: {hex(reg_val)}"
-            val = (val << 1) & 0xff
-            yield
-            yield Settle()
-
-
-
-    sim = Simulator(dut)
-    sim.add_clock(1e-6)
-    sim.add_sync_process(proc1)
-    
-    with sim.write_vcd(filename):
-        sim.run()
-
-
-if __name__ == '__main__':
-    shift_reg = ShiftReg(8)
-    cmd(shift_reg, test_shift_reg)
\ No newline at end of file