consolidated aluflags

1 files changed, 15 insertions, 2 deletions

diff --git a/hdl/core/alu.py b/hdl/core/alu.py
index d9858b1..b4261bd 100644
--- a/hdl/core/alu.py
+++ b/hdl/core/alu.py
@@ -23,6 +23,13 @@ class AluOpCodes(Enum):
     # udiv = 13
     # sdiv = 14
 
+@unique
+class ALUFlags(Enum):
+    zero = 0
+    carry = 1
+    overflow = 2
+    negative = 3
+
 class ALU(Elaboratable):
     def __init__(self, **kargs):
         self.in1 = Signal(32, reset_less=True)
@@ -37,12 +44,13 @@ class ALU(Elaboratable):
         self.zero = Signal(1, reset_less=True)
         self.neg = Signal(1, reset_less=True)
 
+        self.alu_flags = Signal(4, reset_less=True)
         self.out = Signal(32, reset_less=True)
 
         self.sim = kargs["sim"] if "sim" in kargs else None
 
         ports_in = [self.in1, self.in2, self.op, self.c_in]
-        ports_out = [self.c_in, self.out, self.c_out, self.overflow, self.zero, self.neg]
+        ports_out = [self.c_in, self.out, self.alu_flags]
         self.ports = {'in': ports_in, 'out': ports_out}
 
     def elaborate(self, platform=None):
@@ -111,9 +119,14 @@ class ALU(Elaboratable):
         
         m.d.comb += self.c_out.eq(self.tmp[32])
         m.d.comb += self.overflow.eq(self.tmp[32] ^ self.tmp[31])
-        m.d.comb += self.out.eq(self.tmp[0:32])
         m.d.comb += self.neg.eq(self.out[31])
         m.d.comb += self.zero.eq(self.out == 0)
+
+        m.d.comb += self.alu_flags[ALUFlags.zero.value].eq(self.zero)
+        m.d.comb += self.alu_flags[ALUFlags.carry.value].eq(self.c_out)
+        m.d.comb += self.alu_flags[ALUFlags.overflow.value].eq(self.overflow)
+        m.d.comb += self.alu_flags[ALUFlags.negative.value].eq(self.neg)
+        m.d.comb += self.out.eq(self.tmp[0:32])
         
         return m