removed unessary delays in tbs

1 files changed, 9 insertions, 7 deletions

diff --git a/hdl/core/reg.py b/hdl/core/reg.py
index bacf3f1..8815961 100644
--- a/hdl/core/reg.py
+++ b/hdl/core/reg.py
@@ -3,7 +3,7 @@ from amaranth import *
 from amaranth.sim import Settle
 
 from hdl.lib.in_out_buff import InOutBuff
-from hdl.utils import *
+from hdl.utils import cmd, sim, step
 
 from hdl.core.alu import ALUFlags
 
@@ -222,11 +222,13 @@ def test_reg_comb_output():
         for i in range(16):
             yield dut.rs1_addr.eq(i)
             yield Settle()
-            assert (yield dut.rs1) == i, f'ERROR reading {dut.reg_arr[i].name} != {i}'
+            rs1 = yield dut.rs1
+            assert rs1 == i, f'ERROR reading {dut.reg_arr[i].name}: expected {i} != {rs1}'
         for i in range(16):
             yield dut.rs2_addr.eq(i)
             yield Settle()
-            assert (yield dut.rs2) == i, f'ERROR reading {dut.reg_arr[i].name} != {i}'
+            rs2 = yield dut.rs2
+            assert rs2 == i, f'EEROR reading {dut.reg_arr[i].name}: expected {i} != {rs2}'
     sim(dut, proc)
 
 # test writeback with writeback disabled
@@ -237,7 +239,7 @@ def test_reg_writeback_dsb():
         for i in range(16):
             yield dut.rd_addr.eq(i)
             yield dut.rd.eq(i + 1)
-            yield from step()
+            yield 
             if (i != dut.ip.idx) and (i != dut.flg.idx):     # flag gets update by the alu
                 assert (yield dut.reg_arr[i]) == i, f'ERROR writing to {dut.reg_arr[i].name} != {i}'
     sim(dut, proc)
@@ -253,12 +255,12 @@ def test_reg_writeback_en():
             yield dut.rd.eq(i - 1)
             yield from step()
             if (i != dut.zx.idx) and (i != dut.ip.idx):
-                assert (yield dut.reg_arr[i]) == i-1, f'ERROR writing to {dut.reg_arr[i].name} != {i-1}'
+                val = yield dut.reg_arr[i]
+                assert val == i-1, f'ERROR writing to {dut.reg_arr[i].name}, expected {i-1} != {val}'
             elif i == dut.zx.idx:
-                assert (yield dut.zx) == 0, f'ERROR {dut.zx.name} != 0'
+                assert (yield dut.zx) == 0, f'ERROR {dut.zx.name}, expected 0 != {dut.zx}'
             elif i == dut.ip.idx:
                 # ip should be incremented and not written to
-                print((yield dut.ip))
                 assert (yield dut.reg_arr[i]) == dut.ip.idx+4, f'ERROR {dut.ip.name} != {dut.ip.idx+4} should not be able to be directly written to'
     sim(dut, proc)