removed unessary delays in tbs

1 files changed, 14 insertions, 19 deletions

diff --git a/hdl/core/jump_ctl.py b/hdl/core/jump_ctl.py
index 6f02afe..25caf86 100644
--- a/hdl/core/jump_ctl.py
+++ b/hdl/core/jump_ctl.py
@@ -1,8 +1,8 @@
 from amaranth import *
-from amaranth.sim import Simulator, Settle, Delay
+from amaranth.sim import Settle
 from enum import Enum, unique
 
-from hdl.utils import *
+from hdl.utils import sim, cmd, e2s, rand_bits_mix
 from hdl.lib.in_out_buff import InOutBuff   # used for timing analysis
 
 from hdl.core.alu import ALUFlags, ALU, AluOpCodes  #ALUOpCodes is for simulation only, not used in hardware
@@ -36,11 +36,6 @@ class JumpCtl(Elaboratable):
     def elaborate(self, platform=None):
         m = Module()
 
-        # dummy sync for simulation only needed if there is no other sequential logic
-        if self.sim == True:
-            dummy = Signal()
-            m.d.sync += dummy.eq(~dummy)
-
         # xor the bits if both are positive or negative, this is needed to prevent problems with overflow
         diff_sign = Signal(reset_less=True)
         m.d.comb += diff_sign.eq(self.signed_bits.xor())
@@ -115,10 +110,10 @@ def test_jump_eq(tests=NUM_RAND_TESTS):
             in2 = rand_bits_mix(32)
             yield dut.alu.in1.eq(in1)
             yield dut.alu.in2.eq(in2)
-            yield from eval()
+            yield Settle()
             assert (yield dut.jump.cond_true) == (in1 == in2), f"jump_eq failed: in1={hex(in1)}, in2={hex(in2)}, cond_true={(yield dut.jump.cond_true)}"
 
-    sim(dut, proc)
+    sim(dut, proc, sync=False)
 
 # test jump if not equal
 def test_jump_ne(tests=NUM_RAND_TESTS):
@@ -132,10 +127,10 @@ def test_jump_ne(tests=NUM_RAND_TESTS):
                 in2 = rand_bits_mix(32)
                 yield dut.alu.in1.eq(in1)
                 yield dut.alu.in2.eq(in2)
-                yield from eval()
+                yield Settle()
                 assert (yield dut.jump.cond_true) == (in1 != in2), f"jump_ne failed: in1={hex(in1)}, in2={hex(in2)}, cond_true={(yield dut.jump.cond_true)}"
     
-        sim(dut, proc)
+        sim(dut, proc, sync=False)
 
 # test jump if less than unsigned
 def test_jump_lt_u(tests=NUM_RAND_TESTS):
@@ -149,10 +144,10 @@ def test_jump_lt_u(tests=NUM_RAND_TESTS):
                     in2 = rand_bits_mix(32, sus='u')
                     yield dut.alu.in1.eq(in1)
                     yield dut.alu.in2.eq(in2)
-                    yield from eval()
+                    yield Settle()
                     assert (yield dut.jump.cond_true) == (in1 < in2), f"jump_lt_u failed: in1={hex(in1)}, in2={hex(in2)}, cond_true={(yield dut.jump.cond_true)}"
         
-            sim(dut, proc)
+            sim(dut, proc, sync=False)
 
 # test jump if less than or equal to unsigned
 def test_jump_lte_u(tests=NUM_RAND_TESTS):
@@ -166,10 +161,10 @@ def test_jump_lte_u(tests=NUM_RAND_TESTS):
                 in2 = rand_bits_mix(32, sus='u')
                 yield dut.alu.in1.eq(in1)
                 yield dut.alu.in2.eq(in2)
-                yield from eval()
+                yield Settle()
                 assert (yield dut.jump.cond_true) == (in1 <= in2), f"jump_lte_u failed: in1={hex(in1)}, in2={hex(in2)}, cond_true={(yield dut.jump.cond_true)}"
     
-        sim(dut, proc)
+        sim(dut, proc, sync=False)
 
 # test jump if less than signed
 def test_jump_lt_s(tests=NUM_RAND_TESTS):
@@ -183,10 +178,10 @@ def test_jump_lt_s(tests=NUM_RAND_TESTS):
             in2 = rand_bits_mix(32, sus='s')
             yield dut.alu.in1.eq(in1)
             yield dut.alu.in2.eq(in2)
-            yield from eval()
+            yield Settle()
             assert (yield dut.jump.cond_true) == (in1 < in2), f"jump_lt_s failed: in1={hex(in1)}, in2={hex(in2)}, cond_true={(yield dut.jump.cond_true)}"
 
-    sim(dut, proc)
+    sim(dut, proc, sync=False)
 
 # test jump if less than or equal to signed
 def test_jump_lte_s(tests=NUM_RAND_TESTS):
@@ -200,10 +195,10 @@ def test_jump_lte_s(tests=NUM_RAND_TESTS):
             in2 = rand_bits_mix(32, sus='s')
             yield dut.alu.in1.eq(in1)
             yield dut.alu.in2.eq(in2)
-            yield from eval()
+            yield Settle()
             assert (yield dut.jump.cond_true) == (in1 <= in2), f"jump_lte_s failed: in1={hex(in1)}, in2={hex(in2)}, cond_true={(yield dut.jump.cond_true)}"
 
-    sim(dut, proc)
+    sim(dut, proc, sync=False)
 
        
 if __name__ == '__main__':