working on control moduleHEADmaster

1 files changed, 19 insertions, 14 deletions

diff --git a/hdl/core/control.py b/hdl/core/control.py
index d858812..17943d3 100644
--- a/hdl/core/control.py
+++ b/hdl/core/control.py
@@ -1,5 +1,5 @@
 from amaranth import *
-from amaranth.sim import Simulator, Settle, Delay
+from amaranth.sim import Settle, Delay
 from enum import Enum, unique
 
 from hdl.utils import *
@@ -26,6 +26,9 @@ class Control_LUT(Elaboratable):
     def create_lut(self):
         csv_raw = self._read_csv(self.csv_file)
         control_list = self._parse_csv(csv_raw)
+
+        #TODO: Detect duplicate opcodes
+
         mem_width, slice_mapping = self._get_slice_mapping(control_list)
 
         print('debug')
@@ -104,9 +107,9 @@ class Control_LUT(Elaboratable):
             for cl in self.cl_names:
                 try:
                     tmp['data'].append(int(row[cl]))
-                except KeyError:
+                except KeyError as e:
                     print(f'control line "{cl}" not found in csv file')
-                    raise
+                    raise e
 
             csv_parsed.append(tmp)
         return csv_parsed
@@ -114,20 +117,22 @@ class Control_LUT(Elaboratable):
     def _alloc_mem(self, csv_parsed):
         pass
             
-    def _create_init(self, csv_parsed):
-        mem_init = []
+    # def _create_init(self, csv_parsed):
+    #     mem_init = []
+
+    #     for i in range(MAX_INSTR):
+    #         mem_init.append(0)     # init to 0, this sets all op codes to invalid
 
-        for i in range(MAX_INSTR):
-            mem_init.append(0)     # init to 0, this sets all op codes to invalid
+    #     for row in csv_parsed:
+    #         assert(0 <= row['opcode'] < MAX_INSTR), "opcode out of range"
 
-        for row in csv_parsed:
-            assert(0 <= row['opcode'] < MAX_INSTR), "opcode out of range"
-            assert((mem_init[row['opcode']] & 0x1) != 1), 'duplicate opcode, check the .csv file'
+    #         # TODO: fix this to no use static location for valid opcode
+    #         assert((mem_init[row['opcode']] & 0x1) != 1), 'duplicate opcode, check the .csv file'
 
-            for cl in row['data']:
-                mem_init[row['opcode']] = cl
+    #         for cl in row['data']:
+    #             mem_init[row['opcode']] = cl
 
-        return mem_init
+    #     return mem_init
 
 
 class Control(Elaboratable):
@@ -159,7 +164,7 @@ class Control(Elaboratable):
         self.int_en = Signal(1)
         self.user_mode = Signal(1)
 
-        ports_in = [self.instr_op, self.alu_op, self.jump_ctl_op, self.wr_en, self.stall, self.int_sig, self.iret, self.call, self.jump]
+        ports_in = [self.instr_op, self.alu_op, self.jump_ctl_op, self.wb_en, self.stall, self.int_sig, self.iret, self.call, self.jump]
         ports_out = []
         self.ports = {'in': ports_in, 'out': ports_out}