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author | jjsuperpower <jjs29356@gmail.com> | 2022-09-05 20:04:52 -0500 |
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committer | jjsuperpower <jjs29356@gmail.com> | 2022-09-05 20:04:52 -0500 |
commit | 63626f2f6fc7e8912a349f120e37998cd1a05554 (patch) | |
tree | a4a10c448613bd683b79a2f5dbef892edef0d49d /archive/testing/async_reset.py | |
parent | 762e8b8786d8c921726c8ddc92a2513f42dad683 (diff) |
moveing file around
Diffstat (limited to 'archive/testing/async_reset.py')
-rw-r--r-- | archive/testing/async_reset.py | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/archive/testing/async_reset.py b/archive/testing/async_reset.py new file mode 100644 index 0000000..4760df7 --- /dev/null +++ b/archive/testing/async_reset.py @@ -0,0 +1,21 @@ +from amaranth import * +from amaranth.cli import main + + +class ClockDivisor(Elaboratable): + def __init__(self, factor): + self.v = Signal(factor) + self.o = Signal() + + def elaborate(self, platform): + m = Module() + m.d.sync += self.v.eq(self.v + 1) + m.d.comb += self.o.eq(self.v[-1]) + return m + + +if __name__ == "__main__": + m = Module() + m.domains.sync = sync = ClockDomain("sync", async_reset=True) + m.submodules.ctr = ctr = ClockDivisor(factor=16) + main(m, ports=[ctr.o, sync.clk])
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