hdl/testing/simulation/ShiftReg_sim.vcd


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$date
    Fri Jun 24 11:32:38 2022
$end
$version
    MyHDL 0.11
$end
$timescale
    1ns
$end

$scope module tb $end
$var reg 1 ! left_right $end
$var reg 1 " clk $end
$var real 1 # in0 $end
$var reg 8 $ out0 $end
$var reg 1 % reset $end
$scope module ShiftReg0 $end
$var reg 1 % reset $end
$var reg 1 " clk $end
$var real 1 # in0 $end
$var reg 1 ! left_right $end
$var reg 8 $ out0 $end
$upscope $end
$upscope $end

$enddefinitions $end
$dumpvars
0!
0"
s0 #
b00000000 $
0%
$end
#2
1"
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0"
1%
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1"
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0"
s1 #
#10
1"
b00000001 $
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0"
#14
1"
b00000011 $
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0"
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1"
b00000111 $
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0"
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1"
b00001111 $
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0"
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1"
b00011111 $
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0"
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1"
b00111111 $
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0"
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1"
b01111111 $
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0"
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1"
b11111111 $
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0"
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1"
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0"
s0 #
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1"
b11111110 $
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0"
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1"
b11111100 $
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0"
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1"
b11111000 $
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0"
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1"
b11110000 $
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0"
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1"
b11100000 $
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0"
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1"
b11000000 $
#67
#68
0"
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1"
b10000000 $
#71
#72
0"
#74
1"
b00000000 $
#75
#76
0"