import os
from myhdl import *
from constants import *

class Myhdl_Wrapper():
    def __init__(self):
        self.class_name = self.__class__.__name__

    def _export(self, **kargs):
        inst = getattr(self, self.class_name)(**kargs)
        inst.convert(hdl='Verilog', path=GEN_VERILOG, name=f"{self.class_name}")
        


    # This function links myhdl to icarus verilog sim
    def _cosim(self, **kargs): #these should have the same signals as logic(), 

        iverilog_cmd = IVERILOG + f"-o {SIM_DIR}{self.class_name}.o {GEN_VERILOG}{self.class_name}.v {GEN_VERILOG}tb_{self.class_name}.v"
        vvp_cmd = VVP + f"{SIM_DIR}{self.class_name}.o"

        os.system(iverilog_cmd)
        return Cosimulation(vvp_cmd, **kargs)

    def sim(self):
        tb = self.tb(getattr(self, self.class_name))
        tb.config_sim(trace=True, tracebackup=False, directory=SIM_DIR, filename=f"{self.class_name}_sim")
        tb.run_sim()

    def cosim(self):
        tb = self.tb(self._cosim)
        tb.run_sim()