#! /usr/local/bin/vvp
:ivl_version "12.0 (devel)" "(s20150603-1545-g93397e723)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision - 11;
:vpi_module "/usr/local/lib64/ivl/system.vpi";
:vpi_module "/usr/local/lib64/ivl/vhdl_sys.vpi";
:vpi_module "/usr/local/lib64/ivl/vhdl_textio.vpi";
:vpi_module "/usr/local/lib64/ivl/v2005_math.vpi";
:vpi_module "/usr/local/lib64/ivl/va_math.vpi";
S_0x7e78f0 .scope module, "tb_ShiftReg" "tb_ShiftReg" 2 1;
 .timescale -9 -11;
v0x7f96b0_0 .var "clk", 0 0;
v0x7f9770_0 .var "in0", 0 0;
v0x7f9840_0 .var "left_right", 0 0;
v0x7f9940_0 .net "out0", 7 0, v0x7f9420_0;  1 drivers
v0x7f9a10_0 .var "reset", 0 0;
S_0x7e7a80 .scope module, "dut" "ShiftReg" 2 21, 3 8 0, S_0x7e78f0;
 .timescale -9 -11;
    .port_info 0 /INPUT 1 "reset";
    .port_info 1 /INPUT 1 "clk";
    .port_info 2 /INPUT 1 "in0";
    .port_info 3 /OUTPUT 8 "out0";
    .port_info 4 /INPUT 1 "left_right";
v0x7abed0_0 .net "clk", 0 0, v0x7f96b0_0;  1 drivers
v0x7f9290_0 .net "in0", 0 0, v0x7f9770_0;  1 drivers
v0x7f9350_0 .net "left_right", 0 0, v0x7f9840_0;  1 drivers
v0x7f9420_0 .var "out0", 7 0;
v0x7f9500_0 .net "reset", 0 0, v0x7f9a10_0;  1 drivers
E_0x7d0b30/0 .event negedge, v0x7f9500_0;
E_0x7d0b30/1 .event posedge, v0x7abed0_0;
E_0x7d0b30 .event/or E_0x7d0b30/0, E_0x7d0b30/1;
S_0x7abcf0 .scope begin, "SHIFTREG_SHIFTER" "SHIFTREG_SHIFTER" 3 27, 3 27 0, S_0x7e7a80;
 .timescale -9 -11;
    .scope S_0x7e7a80;
T_0 ;
    %wait E_0x7d0b30;
    %fork t_1, S_0x7abcf0;
    %jmp t_0;
    .scope S_0x7abcf0;
t_1 ;
    %load/vec4 v0x7f9500_0;
    %pad/u 32;
    %cmpi/e 0, 0, 32;
    %jmp/0xz  T_0.0, 4;
    %pushi/vec4 0, 0, 8;
    %assign/vec4 v0x7f9420_0, 0;
    %jmp T_0.1;
T_0.0 ;
    %load/vec4 v0x7f9350_0;
    %nor/r;
    %flag_set/vec4 8;
    %jmp/0xz  T_0.2, 8;
    %load/vec4 v0x7f9420_0;
    %parti/s 7, 0, 2;
    %ix/load 4, 1, 0;
    %ix/load 5, 0, 0;
    %flag_set/imm 4, 0;
    %assign/vec4/off/d v0x7f9420_0, 4, 5;
    %load/vec4 v0x7f9290_0;
    %ix/load 4, 0, 0;
    %ix/load 5, 0, 0;
    %flag_set/imm 4, 0;
    %assign/vec4/off/d v0x7f9420_0, 4, 5;
    %jmp T_0.3;
T_0.2 ;
    %load/vec4 v0x7f9420_0;
    %parti/s 7, 1, 2;
    %ix/load 4, 0, 0;
    %ix/load 5, 0, 0;
    %flag_set/imm 4, 0;
    %assign/vec4/off/d v0x7f9420_0, 4, 5;
    %load/vec4 v0x7f9290_0;
    %ix/load 4, 7, 0;
    %ix/load 5, 0, 0;
    %flag_set/imm 4, 0;
    %assign/vec4/off/d v0x7f9420_0, 4, 5;
T_0.3 ;
T_0.1 ;
    %end;
    .scope S_0x7e7a80;
t_0 %join;
    %jmp T_0;
    .thread T_0;
    .scope S_0x7e78f0;
T_1 ;
    %vpi_call 2 10 "$from_myhdl", v0x7f9a10_0, v0x7f96b0_0, v0x7f9770_0, v0x7f9840_0 {0 0 0};
    %vpi_call 2 16 "$to_myhdl", v0x7f9940_0 {0 0 0};
    %end;
    .thread T_1;
# The file index is used to find the file name in the following table.
:file_names 4;
    "N/A";
    "<interactive>";
    "./gen_verilog/tb_ShiftReg.v";
    "./gen_verilog/ShiftReg.v";