from myhdl import *
from random import randrange
import os

from constants import *

class ShiftReg():
    def __init__(self):
        self.class_name = self.__class__.__name__

    # Main code, this is the actual logic
    @staticmethod
    @block
    def ShiftReg(reset: Signal, clk: Signal, in0: Signal, out0: Signal, left_right: Signal):

        width = len(out0)

        @always_seq(clk.posedge, reset=reset)
        def shifter():
            if not left_right:
                out0.next[width:1] = out0[width-1:0]
                out0.next[0] = in0
            else:
                out0.next[width-1:0] = out0[width:1]
                out0.next[width-1] = in0

        return shifter


    @block
    def tb(self, func):
        reset = ResetSignal(0, 0, True)
        clk = Signal(bool(0))
        in0 = Signal(0)
        out0 = Signal(modbv(0)[8:])
        left_right = Signal(bool(0))

        dut = getattr(self, str(func))(reset=reset, clk=clk, in0=in0, out0=out0, left_right=left_right)

        @always(delay(2))
        def clock_gen():
            clk.next = not clk

        @instance
        def monitor():
            while True:
                yield clk.posedge
                yield delay(1)
                print(bin(out0, 8))

        @instance
        def stimulus():
            yield clk.negedge
            reset.next = 1

            for i in range(9):
                yield clk.negedge
                in0.next = 1

            for i in range(9):
                yield clk.negedge
                in0.next = 0

            raise StopSimulation

        return dut, clock_gen, monitor, stimulus

    def convert(self):
        reset = ResetSignal(0, 0, True)
        clk = Signal(bool(0))
        in0 = Signal(bool(0))
        out0 = Signal(modbv(0)[8:])
        left_right = Signal(bool(0))

        inst = self.ShiftReg(reset=reset, clk=clk, in0=in0, out0=out0, left_right=left_right)
        inst.convert(hdl='Verilog', path=GEN_VERILOG, name=f"{self.class_name}")


    # This function links myhdl to icarus verilog sim
    def _cosim(self, **kargs): #these should have the same signals as logic(), 

        iverilog_cmd = IVERILOG + f"-o {SIM_DIR}{self.class_name}.o {GEN_VERILOG}{self.class_name}.v {GEN_VERILOG}tb_{self.class_name}.v"
        vvp_cmd = VVP + f"{SIM_DIR}{self.class_name}.o"

        os.system(iverilog_cmd)
        return Cosimulation(vvp_cmd, **kargs)

    def sim(self):
        tb = self.tb(self.class_name)
        tb.config_sim(trace=True, tracebackup=False, directory=SIM_DIR, filename=f"{self.class_name}_sim")
        tb.run_sim()

    def cosim(self):
        tb = self.tb('_cosim')
        tb.run_sim()


def test_shift_reg():
    hdl = ShiftReg()
    hdl.sim()
    hdl.convert()
    hdl.cosim()


test_shift_reg()