# Vertex KISS 48 - Machine Code Spec ## General Instruction Format X = HEX B = BIN d = HEX (not used / don't care) MAX INSTRUCTIIONS = 256 ALL INSTRUCTIONS ARE ATOMIC ### C-Type, Control XX XX XX XXXXXX Opcode dd RS1 Address/IMM ### I-Type, Immediate XX XX XX XXXXXX Opcode RD RS IMM ### R-Type, Arithmetic XX XXXX XX XX XX Opcode dddd RD RS1 RS2 ### J-Type, Jump / Branch XX XX XXXX XXXX Opcode dd Address (XX * 2^32 + XXXX) ## Registers Maximum registers = 16 Register width = 32 All are R/W except 0X 0X Always Zero AX GP-0 BX GP-1 CX GP-2 DX GP-3 EX GP-4 FX GP-5 GX GP-6 FX GP-7 HI Mult/Div Hi LO Mult/Div Lo FLG Processor Flags CRX Control register (Writable only in supervisor mode) IP Instruction Pointer SP Stack Pointer ### FLG Register Bitfield These registers are Read/Write NOTE: I think this is needed in order to restore from interupt, if this is not true, then I propose the bottom half be read only and the top half be read / write. Then just re-assign the registers to differnt locations FLG[0] Carry FLG[1] Overflow FLG[2] Zero FLG[3] Sign FLG[4]* Interrupt Enable FLG[5]* User Mode FLG[6-31] RESERVED *To be moved to control register* ## Integer Instructions ### R-Type ADD RD, RS1, RS2 RD = RS1 + RS2 SUB RD, RS1, RS2 RD = RS1 - RS2 XOR RD, RS1, RS2 RD = RS1 ^ RS2 OR RD, RS1, RS2 RD = RS1 | RS2 AND RD, RS1, RS2 RD = RS1 & RS2 LSL RD, RS1, RS2 RD = RS1 << RS2 (logical) LSR RD, RS1, RS2 RD = RS1 >> RS2 (logical) ASR RD, RS1, RS2 RD = RS1 >> RS2 MUL RD, RS1, RS2 HI,LO = RS1 * RS2 MULU RD, RS1, RS2 HI,LO = RS1 * RS2 DIV RD, RS1, RS2 HI,LO = RS1 / RS2 DIVU RD, RS1, RS2 HI,LO = RS1 / RS2 (unsigned) LDB RD, RS1, RS2 RD = &(RS1 + RS2) Load Byte STB RD, RS1, RS2 &(RS1 + RS2) = (RD >> 24) Store Byte LDW RD, RS1, RS2 RD = &(RS1 + RS2) Load Word (4 bytes) STW RD, RS1, RS2 &(RS1 + RS2) = RD Store Word (4 bytes) ### I-Type ADDI RD, RS, IMM RD = RS + IMM SUBI RD, RS, IMM RD = RS - IMM XORI RD, RS, IMM RD = RS ^ IMM ORI RD, RS, IMM RD = RS | IMM ANDI RD, RS, IMM RD = RS & IMM LSLI RD, RS, IMM RD = RS << IMM (logical) LSRI RD, RS, IMM RD = RS >> IMM (logical) ASRI RD, RS, IMM RD = RS >> IMM MULI dd, RS, IMM HI,LO = RS * IMM MULIU dd, RS, IMM HI,LO = RS * IMM DIVI dd, RS, IMM HI,LO = RS / IMM DIVIU dd, RS, IMM HI,LO = RS / IMM (unsigned) LDBI RD, RS, RS2 RD = &(RS + IMM) Load Byte STBI RD, RS, RS2 &(RS + IMM) = (RD >> 24) Store Byte LDWI RD, RS, RS2 RD = &(RS + IMM) Load Word (4 bytes) STWI RD, RS, RS2 &(RS + IMM) = RD Store Word (4 bytes) ### Jump Instructions JMP ADDR IP = ADDR JEQ ADDR if (FLG.ZERO == 1) IP = ADDR JLT ADDR if (FLG.SIGN == 0) IP = ADDR JGT* ADDR if (FLG.SIGN == 1) IP = ADDR JLE ADDR if (FLG.ZERO == 1 & FLG.SIGN == 0) IP = ADDR JGE ADDR if (FLG.ZERO == 1 & FLG.SIGN == 1) IP = ADDR JLTU ADDR if (FLG.OVERFLOW == 1) IP = ADDR JGTU ADDR if (FLG.OVERFLOW == 0) IP = ADDR JLEU* ADDR if (FLG.ZERO == 1 & FLG.SIGN == 0) IP = ADDR JGEU* ADDR if (FLG.ZERO == 1 & FLG.SIGN == 1) IP = ADDR *Duplicate OP code* ### Control Instructions NOP Do nothing -> opcode = ZERO PUSHR RS SP+=4;SP = RS POPR RS RS = SP;SP-=4 PUSHI IMM SP+=4;SP = IMM INVP IMM Invalidate entry in TLB RET POPR BX;JMP BX CALL IMM PUSHI $;JMP ADDR INT IMM PUSHR SP;PUSHR FLG;PUSHR IP;PUSHI errno;IP = IDT[IMM] IRET POPR IP;POPR FLG;POPR SP SIF Set interrupt flag CIF Clear interrupt flag ## Interrupt Descriptor Table This will be in a fixed memory location, this will contain pointers to the interupt function. Once an interupt is entered, all interupts are turned off. IDT[0] Divide-by-zero exception IDT[1] Hardware error (NMI) IDT[2] Overflow IDT[3] Invalid Opcode IDT[4] General-protection fault IDT[5] Page fault IDT[6-15] RESERVED IDT[16-255] Platform interrupts (PIC, hard drive, keyboard, etc.) IDT[80] Software interrupt (reserved for OS) ## Page Directory The page directory contains 1024 page tables that have 1024 entries. ### Page table layout PT[0] Present PT[1] R/W PT[2] User-mode PT[3-4] RESERVED PT[5] Accessed PT[6-7] RESERVED PT[8-31] Physical address of page table (XX * 2^16 + XXXX) *This is still WIP but I wanted to get your input on the layout. I also have the jank memory offset that will more than likely change.*