# Vertex KISS 32 - Machine Code Spec ^ So Vertex is already a name for an FPGA, should we change this? I propose a different name: ASAP Soc 32 a KISS architecture As Simple As Possible ## General Instruction Format X = HEX B = BIN MAX INSTRUCTIIONS = 256 ALL INSTRUCTIONS ARE ATOMIC ### C-Type, Control XX X X XXXX Opcode d RS1 IMM ### I-Type, Immediate XX X X XXXX Opcode RD RS1 IMM ### R-Type, Arithmetic XX X X X XXX Opcode RD RS1 RS2 ddd ### JR-Type, Compare and Jump XX X X X XXX Opcode Jump Condition RS1 RS2 ddd ### JI-Type, Compare and Jump XX X X XXXX Opcode Jump Condition RS1 IMM ## Registers Maximum registers = 16 Register width = 32 All are R/W except 0X 0X Always Zero AX GP-0 BX GP-1 CX GP-2 DX GP-3 EX GP-4 FX GP-5 GX GP-6 HX GP-7 IP Instruction Pointer SP Stack Pointer FLG Processor Flags CS0 Control status 0 (saves IP) CS1 Control status 1 (saves SP) CS2 Control status 2 (saves FLG) PDA Page Directory Address ### FLG Flag Register Bitfield The lower half is read/write The upper half can be read or written to in supervisor mode only FLG[0] Carry FLG[1] Overflow FLG[2] Zero FLG[3] Sign FLG[4] Odd (parity) FLG[5-15] RESERVED FLG[16] Interrupt enable* FLG[17] User mode* FLG[18] Paging enabled* FLG[19-31] RESERVED* *Must be in supervisor mode (FLG[17]=0) to set ## Integer Instructions ### R-Type ADD RD, RS1, RS2 RD = RS1 + RS2 SUB RD, RS1, RS2 RD = RS1 - RS2 XOR RD, RS1, RS2 RD = RS1 ^ RS2 OR RD, RS1, RS2 RD = RS1 | RS2 AND RD, RS1, RS2 RD = RS1 & RS2 LSL RD, RS1, RS2 RD = RS1 << RS2 (logical) LSR RD, RS1, RS2 RD = RS1 >> RS2 (logical) ASR RD, RS1, RS2 RD = RS1 >> RS2 MUL RD, RS1, RS2 RD = RS1 * RS2 MULU RD, RS1, RS2 RD = RS1 * RS2 (unsigned) DIV RD, RS1, RS2 RD = RS1 / RS2 DIVU RD, RS1, RS2 RD = RS1 / RS2 (unsigned) *DIV is based on shift-and-multiply algorithm *DIV Ex: 8000/192 (8000/64)/3 (8000>>6)/3 (8000>>6)*0x5555>>16=41 ### I-Type ADDI RD, RS, IMM RD = RS + IMM SUBI RD, RS, IMM RD = RS - IMM XORI RD, RS, IMM RD = RS ^ IMM ORI RD, RS, IMM RD = RS | IMM ANDI RD, RS, IMM RD = RS & IMM LSLI RD, RS, IMM RD = RS << IMM (logical) LSRI RD, RS, IMM RD = RS >> IMM (logical) ASRI RD, RS, IMM RD = RS >> IMM DIVI RD, RS, IMM RD = RS / IMM DIVIU RD, RS, IMM RD = RS / IMM (unsigned) ### JR Instructions JMP 0 if (True) JMP 1 if (RS1 != RS2) JMP 2 if (RS1 == RS2) JMP 3 if (RS1 > RS2) Unsigned JMP 4 if (RS1 >= RS2) Unsigned JMP C if (RS1 > RS2) Signed JMP D if (RS1 >= RS2) Signed ### JI Instructions Compare and then jump (IP = JMP) JMPI 0 if (True) JMPI 1 if (RS1 != IMM) JMPI 2 if (RS1 == IMM) JMPI 3 if (RS1 > IMM) Unsigned JMPI 4 if (RS1 >= IMM) Unsigned JMPI C if (RS1 > IMM) Signed JMPI D if (RS1 >= IMM) Signed ### Jump Aliases JEQ JLT JGT JLE JGE JLTU JGTU JLEU JGEU ### Control Instructions NOP Do nothing -> opcode = ZERO HLT Spinlock the CPU* PUSHR RS SP+=1 ;*SP = RS POPR RS RS = *SP ;SP-=1 PUSHI IMM SP+=1 ;*SP = IMM INVP IMM Invalidate entry in TLB* JMP IMM Jump to address IMM CALL LABEL CS0=IP; IP=LABEL INT IMM CS0=IP; CS1=SP; CS2=FLG; IP=IDT[IMM]* SCALL Same as call but is used to make calls to the kernel (fixed IDT address) IRET IP=CS0; SP=CS1; FLG=CS2* RET IP = CS0 SIF Set interrupt flag* CIF Clear interrupt flag* *Requires processor to be in supervisor mode (FLG[17]=0) ## Interrupt Descriptor Table This will be in a fixed memory location, this will contain pointers to the interupt function. IDT[0] Divide-by-zero exception IDT[1] Hardware error (NMI) IDT[2] Overflow IDT[3] Invalid Opcode IDT[4] General-protection fault IDT[5] Page fault IDT[6] Software interrupt (reserved for OS) IDT[7-31] RESERVED IDT[32-255] Platform interrupts (PIC, hard drive, keyboard, etc.) ## Page Directory The page directory contains 1024 page tables that have 1024 entries that are 4096 bytes wide. Optionally, the page table can be 4MB bytes wide with a setting in the page table. If this bit is set, there is 1024 entries in the page directory; otherwise, there are 2^20 entries. ### Page table layout PT[0] Present PT[1] R/W PT[2] User-mode PT[3] Accessed PT[4] Dirty PT[5] PWT PT[6] Cache-disable PT[7] Page size (0=4KB 1=4MB) PT[8-31] Physical address of page