import os
from myhdl import *
from constants import *

class Myhdl_Wrapper():
    def __init__(self):
        self.class_name = self.__class__.__name__

    def _export(self, **kargs):
        inst = getattr(self, self.class_name)(**kargs)
        inst.convert(hdl='Verilog', path=GEN_VERILOG, name=f"{self.class_name}")

        test_bench_file = GEN_VERILOG + 'tb_' +self.class_name + '.v'
        test_bench_tmp_file = GEN_VERILOG + '~tb_' +self.class_name + '.v'

        # this is needed to generate cosim vcd file
        with open(test_bench_file) as f_old, open(test_bench_tmp_file, 'w') as f_new:
            lines =  f_old.readlines()
            for line in lines:
                f_new.write(line)
                if 'initial begin' in line:
                    f_new.write('\n')
                    f_new.write('    // Needed to create vcd file\n')
                    f_new.write(f'    $dumpfile ("{SIM_DIR + self.class_name}_cosim.vcd");\n')
                    f_new.write(f'    $dumpvars(0, tb_{self.class_name});\n')
                    f_new.write('\n')
        os.rename(test_bench_tmp_file, test_bench_file)
        


    # This function links myhdl to icarus verilog sim
    def _cosim(self, **kargs): #these should have the same signals as logic(), 

        iverilog_cmd = IVERILOG + f"-o {SIM_DIR}{self.class_name}.o {GEN_VERILOG}{self.class_name}.v {GEN_VERILOG}tb_{self.class_name}.v"
        vvp_cmd = VVP + f"{SIM_DIR}{self.class_name}.o"

        os.system(iverilog_cmd)
        return Cosimulation(vvp_cmd, **kargs)

    def sim(self):
        tb = self.tb(getattr(self, self.class_name))
        tb.config_sim(trace=True, tracebackup=False, directory=SIM_DIR, filename=f"{self.class_name}_sim")
        tb.run_sim()

    def cosim(self):
        tb = self.tb(self._cosim)
        tb.run_sim()