From 5de4d07c6db81a9ed21cd39aaef229fb94c4bb6b Mon Sep 17 00:00:00 2001 From: jjsuperpower Date: Sun, 26 Jun 2022 11:11:43 -0500 Subject: added template --- hdl_lab/hdl/myhdl_wrap.py | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 hdl_lab/hdl/myhdl_wrap.py (limited to 'hdl_lab/hdl/myhdl_wrap.py') diff --git a/hdl_lab/hdl/myhdl_wrap.py b/hdl_lab/hdl/myhdl_wrap.py new file mode 100644 index 0000000..2e8fe4e --- /dev/null +++ b/hdl_lab/hdl/myhdl_wrap.py @@ -0,0 +1,31 @@ +import os +from myhdl import * +from constants import * + +class Myhdl_Wrapper(): + def __init__(self): + self.class_name = self.__class__.__name__ + + def _export(self, **kargs): + inst = getattr(self, self.class_name)(**kargs) + inst.convert(hdl='Verilog', path=GEN_VERILOG, name=f"{self.class_name}") + + + + # This function links myhdl to icarus verilog sim + def _cosim(self, **kargs): #these should have the same signals as logic(), + + iverilog_cmd = IVERILOG + f"-o {SIM_DIR}{self.class_name}.o {GEN_VERILOG}{self.class_name}.v {GEN_VERILOG}tb_{self.class_name}.v" + vvp_cmd = VVP + f"{SIM_DIR}{self.class_name}.o" + + os.system(iverilog_cmd) + return Cosimulation(vvp_cmd, **kargs) + + def sim(self): + tb = self.tb(getattr(self, self.class_name)) + tb.config_sim(trace=True, tracebackup=False, directory=SIM_DIR, filename=f"{self.class_name}_sim") + tb.run_sim() + + def cosim(self): + tb = self.tb(self._cosim) + tb.run_sim() \ No newline at end of file -- cgit v1.2.3