From af47ba80d5db24163feb378c52a20639e2532580 Mon Sep 17 00:00:00 2001 From: jjsuperpower Date: Fri, 24 Jun 2022 11:40:10 -0500 Subject: before myhdl_wraper --- hdl/testing/__pycache__/shift_reg.cpython-38.pyc | Bin 0 -> 3474 bytes hdl/testing/delme.py | 11 ++ hdl/testing/myhdl_wrap.py | 0 hdl/testing/shift_reg.py | 26 +++-- hdl/testing/simulation/ShiftReg.o | 77 +++++++----- hdl/testing/simulation/ShiftReg_sim.vcd | 143 ++++++++++++----------- 6 files changed, 147 insertions(+), 110 deletions(-) create mode 100644 hdl/testing/__pycache__/shift_reg.cpython-38.pyc create mode 100644 hdl/testing/delme.py create mode 100644 hdl/testing/myhdl_wrap.py (limited to 'hdl') diff --git a/hdl/testing/__pycache__/shift_reg.cpython-38.pyc b/hdl/testing/__pycache__/shift_reg.cpython-38.pyc new file mode 100644 index 0000000..7a2f246 Binary files /dev/null and b/hdl/testing/__pycache__/shift_reg.cpython-38.pyc differ diff --git a/hdl/testing/delme.py b/hdl/testing/delme.py new file mode 100644 index 0000000..1264357 --- /dev/null +++ b/hdl/testing/delme.py @@ -0,0 +1,11 @@ +class A(): + def __init__(self): + print(f"Parent Class: {self.__class__}") + +class B(A): + def __init__(self): + super().__init__() + print(f"Child Class: {self.__class__}") + + +b = B() \ No newline at end of file diff --git a/hdl/testing/myhdl_wrap.py b/hdl/testing/myhdl_wrap.py new file mode 100644 index 0000000..e69de29 diff --git a/hdl/testing/shift_reg.py b/hdl/testing/shift_reg.py index c27b0f7..de2ed3f 100644 --- a/hdl/testing/shift_reg.py +++ b/hdl/testing/shift_reg.py @@ -11,11 +11,13 @@ class ShiftReg(): # Main code, this is the actual logic @staticmethod @block - def ShiftReg(reset: Signal, clk: Signal, in0: Signal, out0: Signal, left_rigt: bool = 0, width: int = 8): + def ShiftReg(reset: Signal, clk: Signal, in0: Signal, out0: Signal, left_right: Signal): + + width = len(out0) @always_seq(clk.posedge, reset=reset) def shifter(): - if not left_rigt: + if not left_right: out0.next[width:1] = out0[width-1:0] out0.next[0] = in0 else: @@ -31,8 +33,9 @@ class ShiftReg(): clk = Signal(bool(0)) in0 = Signal(0) out0 = Signal(modbv(0)[8:]) + left_right = Signal(bool(0)) - dut = getattr(self, str(func))(reset=reset, clk=clk, in0=in0, out0=out0) + dut = getattr(self, str(func))(reset=reset, clk=clk, in0=in0, out0=out0, left_right=left_right) @always(delay(2)) def clock_gen(): @@ -67,27 +70,23 @@ class ShiftReg(): clk = Signal(bool(0)) in0 = Signal(bool(0)) out0 = Signal(modbv(0)[8:]) + left_right = Signal(bool(0)) - inst = self.logic(reset=reset, clk=clk, in0=in0, out0=out0) + inst = self.ShiftReg(reset=reset, clk=clk, in0=in0, out0=out0, left_right=left_right) inst.convert(hdl='Verilog', path=GEN_VERILOG, name=f"{self.class_name}") # This function links myhdl to icarus verilog sim - def _cosim(self, reset: Signal, clk: Signal, in0: Signal, out0: Signal): #these should have the same signals as logic(), + def _cosim(self, **kargs): #these should have the same signals as logic(), iverilog_cmd = IVERILOG + f"-o {SIM_DIR}{self.class_name}.o {GEN_VERILOG}{self.class_name}.v {GEN_VERILOG}tb_{self.class_name}.v" vvp_cmd = VVP + f"{SIM_DIR}{self.class_name}.o" - signals = locals() - signals.pop('self', None) - signals.pop('iverilog_cmd', None) - signals.pop('vvp_cmd', None) - os.system(iverilog_cmd) - return Cosimulation(vvp_cmd, **signals) + return Cosimulation(vvp_cmd, **kargs) def sim(self): - tb = self.tb('logic') + tb = self.tb(self.class_name) tb.config_sim(trace=True, tracebackup=False, directory=SIM_DIR, filename=f"{self.class_name}_sim") tb.run_sim() @@ -101,3 +100,6 @@ def test_shift_reg(): hdl.sim() hdl.convert() hdl.cosim() + + +test_shift_reg() \ No newline at end of file diff --git a/hdl/testing/simulation/ShiftReg.o b/hdl/testing/simulation/ShiftReg.o index e5d3c84..80f6349 100755 --- a/hdl/testing/simulation/ShiftReg.o +++ b/hdl/testing/simulation/ShiftReg.o @@ -7,63 +7,84 @@ :vpi_module "/usr/local/lib64/ivl/vhdl_textio.vpi"; :vpi_module "/usr/local/lib64/ivl/v2005_math.vpi"; :vpi_module "/usr/local/lib64/ivl/va_math.vpi"; -S_0xf39680 .scope module, "tb_ShiftReg" "tb_ShiftReg" 2 1; +S_0x7e78f0 .scope module, "tb_ShiftReg" "tb_ShiftReg" 2 1; .timescale -9 -11; -v0xf4a460_0 .var "clk", 0 0; -v0xf4a520_0 .var "in0", 0 0; -v0xf4a5f0_0 .net "out0", 7 0, v0xf4a200_0; 1 drivers -v0xf4a6f0_0 .var "reset", 0 0; -S_0xf39810 .scope module, "dut" "ShiftReg" 2 19, 3 8 0, S_0xf39680; +v0x7f96b0_0 .var "clk", 0 0; +v0x7f9770_0 .var "in0", 0 0; +v0x7f9840_0 .var "left_right", 0 0; +v0x7f9940_0 .net "out0", 7 0, v0x7f9420_0; 1 drivers +v0x7f9a10_0 .var "reset", 0 0; +S_0x7e7a80 .scope module, "dut" "ShiftReg" 2 21, 3 8 0, S_0x7e78f0; .timescale -9 -11; .port_info 0 /INPUT 1 "reset"; .port_info 1 /INPUT 1 "clk"; .port_info 2 /INPUT 1 "in0"; .port_info 3 /OUTPUT 8 "out0"; -v0xf39a60_0 .net "clk", 0 0, v0xf4a460_0; 1 drivers -v0xf4a140_0 .net "in0", 0 0, v0xf4a520_0; 1 drivers -v0xf4a200_0 .var "out0", 7 0; -v0xf4a2f0_0 .net "reset", 0 0, v0xf4a6f0_0; 1 drivers -E_0xf23bd0/0 .event negedge, v0xf4a2f0_0; -E_0xf23bd0/1 .event posedge, v0xf39a60_0; -E_0xf23bd0 .event/or E_0xf23bd0/0, E_0xf23bd0/1; -S_0xefdcf0 .scope begin, "SHIFTREG_SHIFTER" "SHIFTREG_SHIFTER" 3 25, 3 25 0, S_0xf39810; + .port_info 4 /INPUT 1 "left_right"; +v0x7abed0_0 .net "clk", 0 0, v0x7f96b0_0; 1 drivers +v0x7f9290_0 .net "in0", 0 0, v0x7f9770_0; 1 drivers +v0x7f9350_0 .net "left_right", 0 0, v0x7f9840_0; 1 drivers +v0x7f9420_0 .var "out0", 7 0; +v0x7f9500_0 .net "reset", 0 0, v0x7f9a10_0; 1 drivers +E_0x7d0b30/0 .event negedge, v0x7f9500_0; +E_0x7d0b30/1 .event posedge, v0x7abed0_0; +E_0x7d0b30 .event/or E_0x7d0b30/0, E_0x7d0b30/1; +S_0x7abcf0 .scope begin, "SHIFTREG_SHIFTER" "SHIFTREG_SHIFTER" 3 27, 3 27 0, S_0x7e7a80; .timescale -9 -11; - .scope S_0xf39810; + .scope S_0x7e7a80; T_0 ; - %wait E_0xf23bd0; - %fork t_1, S_0xefdcf0; + %wait E_0x7d0b30; + %fork t_1, S_0x7abcf0; %jmp t_0; - .scope S_0xefdcf0; + .scope S_0x7abcf0; t_1 ; - %load/vec4 v0xf4a2f0_0; + %load/vec4 v0x7f9500_0; %pad/u 32; %cmpi/e 0, 0, 32; %jmp/0xz T_0.0, 4; %pushi/vec4 0, 0, 8; - %assign/vec4 v0xf4a200_0, 0; + %assign/vec4 v0x7f9420_0, 0; %jmp T_0.1; T_0.0 ; - %load/vec4 v0xf4a200_0; + %load/vec4 v0x7f9350_0; + %nor/r; + %flag_set/vec4 8; + %jmp/0xz T_0.2, 8; + %load/vec4 v0x7f9420_0; + %parti/s 7, 0, 2; + %ix/load 4, 1, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x7f9420_0, 4, 5; + %load/vec4 v0x7f9290_0; + %ix/load 4, 0, 0; + %ix/load 5, 0, 0; + %flag_set/imm 4, 0; + %assign/vec4/off/d v0x7f9420_0, 4, 5; + %jmp T_0.3; +T_0.2 ; + %load/vec4 v0x7f9420_0; %parti/s 7, 1, 2; %ix/load 4, 0, 0; %ix/load 5, 0, 0; %flag_set/imm 4, 0; - %assign/vec4/off/d v0xf4a200_0, 4, 5; - %load/vec4 v0xf4a140_0; + %assign/vec4/off/d v0x7f9420_0, 4, 5; + %load/vec4 v0x7f9290_0; %ix/load 4, 7, 0; %ix/load 5, 0, 0; %flag_set/imm 4, 0; - %assign/vec4/off/d v0xf4a200_0, 4, 5; + %assign/vec4/off/d v0x7f9420_0, 4, 5; +T_0.3 ; T_0.1 ; %end; - .scope S_0xf39810; + .scope S_0x7e7a80; t_0 %join; %jmp T_0; .thread T_0; - .scope S_0xf39680; + .scope S_0x7e78f0; T_1 ; - %vpi_call 2 9 "$from_myhdl", v0xf4a6f0_0, v0xf4a460_0, v0xf4a520_0 {0 0 0}; - %vpi_call 2 14 "$to_myhdl", v0xf4a5f0_0 {0 0 0}; + %vpi_call 2 10 "$from_myhdl", v0x7f9a10_0, v0x7f96b0_0, v0x7f9770_0, v0x7f9840_0 {0 0 0}; + %vpi_call 2 16 "$to_myhdl", v0x7f9940_0 {0 0 0}; %end; .thread T_1; # The file index is used to find the file name in the following table. diff --git a/hdl/testing/simulation/ShiftReg_sim.vcd b/hdl/testing/simulation/ShiftReg_sim.vcd index f9d6dd4..059b493 100644 --- a/hdl/testing/simulation/ShiftReg_sim.vcd +++ b/hdl/testing/simulation/ShiftReg_sim.vcd @@ -1,5 +1,5 @@ $date - Thu Jun 23 23:03:17 2022 + Fri Jun 24 11:32:38 2022 $end $version MyHDL 0.11 @@ -9,136 +9,139 @@ $timescale $end $scope module tb $end -$var reg 1 ! clk $end -$var real 1 " in0 $end -$var reg 8 # out0 $end -$var reg 1 $ reset $end -$scope module logic0 $end -$var reg 1 $ reset $end -$var reg 1 ! clk $end -$var real 1 " in0 $end -$var reg 8 # out0 $end +$var reg 1 ! left_right $end +$var reg 1 " clk $end +$var real 1 # in0 $end +$var reg 8 $ out0 $end +$var reg 1 % reset $end +$scope module ShiftReg0 $end +$var reg 1 % reset $end +$var reg 1 " clk $end +$var real 1 # in0 $end +$var reg 1 ! left_right $end +$var reg 8 $ out0 $end $upscope $end $upscope $end $enddefinitions $end $dumpvars 0! -s0 " -b00000000 # -0$ +0" +s0 # +b00000000 $ +0% $end #2 -1! +1" #3 #4 -0! -1$ +0" +1% #6 -1! +1" #7 #8 -0! -s1 " +0" +s1 # #10 -1! -b10000000 # +1" +b00000001 $ #11 #12 -0! +0" #14 -1! -b11000000 # +1" +b00000011 $ #15 #16 -0! +0" #18 -1! -b11100000 # +1" +b00000111 $ #19 #20 -0! +0" #22 -1! -b11110000 # +1" +b00001111 $ #23 #24 -0! +0" #26 -1! -b11111000 # +1" +b00011111 $ #27 #28 -0! +0" #30 -1! -b11111100 # +1" +b00111111 $ #31 #32 -0! +0" #34 -1! -b11111110 # +1" +b01111111 $ #35 #36 -0! +0" #38 -1! -b11111111 # +1" +b11111111 $ #39 #40 -0! +0" #42 -1! +1" #43 #44 -0! -s0 " +0" +s0 # #46 -1! -b01111111 # +1" +b11111110 $ #47 #48 -0! +0" #50 -1! -b00111111 # +1" +b11111100 $ #51 #52 -0! +0" #54 -1! -b00011111 # +1" +b11111000 $ #55 #56 -0! +0" #58 -1! -b00001111 # +1" +b11110000 $ #59 #60 -0! +0" #62 -1! -b00000111 # +1" +b11100000 $ #63 #64 -0! +0" #66 -1! -b00000011 # +1" +b11000000 $ #67 #68 -0! +0" #70 -1! -b00000001 # +1" +b10000000 $ #71 #72 -0! +0" #74 -1! -b00000000 # +1" +b00000000 $ #75 #76 -0! +0" -- cgit v1.2.3