From aac788e03219309ae43a0296c773a10a94cfe9f7 Mon Sep 17 00:00:00 2001 From: jjsuperpower Date: Sat, 29 Apr 2023 00:34:07 -0500 Subject: removed unessary delays in tbs --- hdl/core/alu.py | 58 +++++++++++++++++++++++----------------------------- hdl/core/jump_ctl.py | 33 +++++++++++++----------------- hdl/core/reg.py | 16 ++++++++------- hdl/lib/shift_reg.py | 10 ++++----- hdl/utils.py | 13 ++++++++---- 5 files changed, 63 insertions(+), 67 deletions(-) (limited to 'hdl') diff --git a/hdl/core/alu.py b/hdl/core/alu.py index 789c26e..4380b8e 100644 --- a/hdl/core/alu.py +++ b/hdl/core/alu.py @@ -2,7 +2,7 @@ from amaranth import * from amaranth.sim import Simulator, Settle, Delay from enum import Enum, unique -from hdl.utils import * +from hdl.utils import sim, e2s, cmd, rand_bits_mix from hdl.lib.in_out_buff import InOutBuff from hdl.config import NUM_RAND_TESTS @@ -49,7 +49,7 @@ class ALU(Elaboratable): self.alu_flags = Signal(len(ALUFlags), reset_less=True) # alu flags is one hot self.out = Signal(32, reset_less=True) - self.sim = kargs["sim"] if "sim" in kargs else None + self.sim = kargs.get('sim', False) ports_in = [self.in1, self.in2, self.op, self.c_in] ports_out = [self.c_in, self.out, self.alu_flags] @@ -58,11 +58,6 @@ class ALU(Elaboratable): def elaborate(self, platform=None): m = Module() - # dummy sync for simulation only - if self.sim == True: - dummy = Signal() - m.d.sync += dummy.eq(~dummy) - with m.Switch(self.op): with m.Case(AluOpCodes.add.value): m.d.comb += self.tmp.eq(self.in1 + self.in2) @@ -142,7 +137,6 @@ def sub_proc(dut, val1, val2, c_in=0): yield dut.in1.eq(val1) yield dut.in2.eq(val2) yield dut.c_in.eq(c_in) - yield yield Settle() # test addition @@ -153,7 +147,7 @@ def test_alu_add(): yield from sub_proc(dut, 27, 13) out = yield dut.out assert 27 + 13 == (out), f'ERROR: {out} != {27 + 13}' - sim(dut, proc) + sim(dut, proc, sync=False) # test addition with carry def test_alu_addc(): @@ -163,7 +157,7 @@ def test_alu_addc(): yield from sub_proc(dut, 11, 43, 1) out = yield dut.out.as_signed() assert 11 + 43 + 1 == out, f'ERROR: {out} != {11 + 43 + 1}' - sim(dut, proc) + sim(dut, proc, sync=False) # test subtraction def test_alu_sub(): @@ -173,7 +167,7 @@ def test_alu_sub(): yield from sub_proc(dut, 25, 13) out = yield dut.out assert 25 - 13 == out, f'ERROR: {out} != {25 - 13}' - sim(dut, proc) + sim(dut, proc, sync=False) # test subtraction with carry def test_alu_subc_0(): @@ -183,7 +177,7 @@ def test_alu_subc_0(): yield from sub_proc(dut, 25, -13, 0) out = yield dut.out.as_signed() assert 25 + 13 -1 +0 == out, f'ERROR: {out} != {25 + 13 -1 +0}' - sim(dut, proc) + sim(dut, proc, sync=False) # test subtraction with carry def test_alu_subc_1(): @@ -193,7 +187,7 @@ def test_alu_subc_1(): yield from sub_proc(dut, 25, -13, 1) out = yield dut.out.as_signed() assert 25 + 13 -1 +1 == out, f'ERROR: {out} != {25 + 13 -1 +1}' - sim(dut, proc) + sim(dut, proc, sync=False) # test binary and def test_alu_and(): @@ -203,7 +197,7 @@ def test_alu_and(): yield from sub_proc(dut, 0b10101011, 0b01010101) out = yield dut.out assert 0b00000001 == out, f'ERROR: {out} != {0b00000001}' - sim(dut, proc) + sim(dut, proc, sync=False) # test binary or def test_alu_or(): @@ -213,7 +207,7 @@ def test_alu_or(): yield from sub_proc(dut, 0b10101011, 0b01000101) out = yield dut.out assert 0b11101111 == out, f'ERROR: {out} != {0b11101111}' - sim(dut, proc) + sim(dut, proc, sync=False) # test binary nor def test_alu_nor(): @@ -223,7 +217,7 @@ def test_alu_nor(): yield from sub_proc(dut, 0b10001011, 0b01000101) out = yield dut.out assert 0b11111111111111111111111100110000 == out, f'ERROR: {bin(out)} != {bin(0b11111111111111111111111100110000)}' - sim(dut, proc) + sim(dut, proc, sync=False) # test binary xor def test_alu_xor(): @@ -233,7 +227,7 @@ def test_alu_xor(): yield from sub_proc(dut, 0b10001011, 0b01000101) out = yield dut.out assert 0b11001110 == out, f'ERROR: {out} != {0b11001110}' - sim(dut, proc) + sim(dut, proc, sync=False) # test logical shift left def test_alu_logic_shift_left(): @@ -245,7 +239,7 @@ def test_alu_logic_shift_left(): assert 0b00010110000000000000000000000000 == out, f'ERROR: {bin(out)} != {bin(0b00010110000000000000000000000000)}' out = yield dut.c_out assert 1 == out, f'ERROR: {out} != {1}' - sim(dut, proc) + sim(dut, proc, sync=False) # test logical shift right def test_alu_logic_shift_right(): @@ -257,7 +251,7 @@ def test_alu_logic_shift_right(): assert 0b1000 == out, f'ERROR: {bin(out)} != {bin(0b1000)}' out = yield dut.c_out assert 1 == out, f'ERROR: {out} != {1}' - sim(dut, proc) + sim(dut, proc, sync=False) # test arithmetic shift right def test_alu_arith_shift_right(): @@ -269,7 +263,7 @@ def test_alu_arith_shift_right(): assert 0xF8000123 == out, f'ERROR: {out} != {0xF8000123}' out = yield dut.c_out assert 0 == out, f'ERROR: {out} != {0}' - sim(dut, proc) + sim(dut, proc, sync=False) # test low unsigned multiply def test_alu_mul_low_u(tests=NUM_RAND_TESTS): @@ -283,11 +277,11 @@ def test_alu_mul_low_u(tests=NUM_RAND_TESTS): in2 = rand_bits_mix(32, sus='u') yield dut.in1.eq(in1) yield dut.in2.eq(in2) - yield from eval() + yield Settle() expected = (in1 * in2) & 0xFFFFFFFF assert (yield dut.out) == expected, f"mul_low_u failed: in1={hex(in1)}, in2={hex(in2)}, out={hex((yield dut.out))}, expected={hex(expected)}" - sim(dut, proc) + sim(dut, proc, sync=False) # test high unsigned multiply def test_alu_mul_high_u(tests=NUM_RAND_TESTS): @@ -301,11 +295,11 @@ def test_alu_mul_high_u(tests=NUM_RAND_TESTS): in2 = rand_bits_mix(32, sus='u') yield dut.in1.eq(in1) yield dut.in2.eq(in2) - yield from eval() + yield Settle() expected = ((in1 * in2) >> 32) & 0xFFFFFFFF assert (yield dut.out) == expected, f"mul_high_u failed: in1={hex(in1)}, in2={hex(in2)}, out={hex((yield dut.out))}, expected={hex(expected)}" - sim(dut, proc) + sim(dut, proc, sync=False) # test low signed multiply def test_alu_mul_low_s(tests=NUM_RAND_TESTS): @@ -319,11 +313,11 @@ def test_alu_mul_low_s(tests=NUM_RAND_TESTS): in2 = rand_bits_mix(32, sus='s') yield dut.in1.eq(in1) yield dut.in2.eq(in2) - yield from eval() + yield Settle() expected = (in1 * in2) & 0xFFFFFFFF assert (yield dut.out) == expected, f"mul_low_s failed: in1={hex(in1)}, in2={hex(in2)}, out={hex((yield dut.out))}, expected={hex(expected)}" - sim(dut, proc) + sim(dut, proc, sync=False) # test high signed multiply def test_alu_mul_high_s(tests=NUM_RAND_TESTS): @@ -337,11 +331,11 @@ def test_alu_mul_high_s(tests=NUM_RAND_TESTS): in2 = rand_bits_mix(32, sus='s') yield dut.in1.eq(in1) yield dut.in2.eq(in2) - yield from eval() + yield Settle() expected = ((in1 * in2) >> 32) & 0xFFFFFFFF assert (yield dut.out) == expected, f"mul_high_s failed: in1={hex(in1)}, in2={hex(in2)}, out={hex((yield dut.out))}, expected={hex(expected)}" - sim(dut, proc) + sim(dut, proc, sync=False) # test unsigned overflow @@ -354,7 +348,7 @@ def test_alu_unsigned_overflow(): assert out == 1, f'ERROR: {out} != {1}' out = yield dut.c_out assert out == 1, f'ERROR: {out} != {1}' - sim(dut, proc) + sim(dut, proc, sync=False) # test unsigned underflow def test_alu_unsigned_underflow(): @@ -366,7 +360,7 @@ def test_alu_unsigned_underflow(): assert out == 1, f'ERROR: {out} != {1}' out = yield dut.c_out assert out == 0, f'ERROR: {out} != {0}' - sim(dut, proc) + sim(dut, proc, sync=False) # test zero def test_alu_zero_0(): @@ -376,7 +370,7 @@ def test_alu_zero_0(): yield from sub_proc(dut, 0, 1) # add 0 to 0 out = yield dut.zero assert out == 0, f'ERROR: {out} != {0}' - sim(dut, proc) + sim(dut, proc, sync=False) # test zero def test_alu_zero_1(): @@ -386,7 +380,7 @@ def test_alu_zero_1(): yield from sub_proc(dut, 0, 0) # add 0 to 0 out = yield dut.zero assert out == 1, f'ERROR: {out} != {1}' - sim(dut, proc) + sim(dut, proc, sync=False) diff --git a/hdl/core/jump_ctl.py b/hdl/core/jump_ctl.py index 6f02afe..25caf86 100644 --- a/hdl/core/jump_ctl.py +++ b/hdl/core/jump_ctl.py @@ -1,8 +1,8 @@ from amaranth import * -from amaranth.sim import Simulator, Settle, Delay +from amaranth.sim import Settle from enum import Enum, unique -from hdl.utils import * +from hdl.utils import sim, cmd, e2s, rand_bits_mix from hdl.lib.in_out_buff import InOutBuff # used for timing analysis from hdl.core.alu import ALUFlags, ALU, AluOpCodes #ALUOpCodes is for simulation only, not used in hardware @@ -36,11 +36,6 @@ class JumpCtl(Elaboratable): def elaborate(self, platform=None): m = Module() - # dummy sync for simulation only needed if there is no other sequential logic - if self.sim == True: - dummy = Signal() - m.d.sync += dummy.eq(~dummy) - # xor the bits if both are positive or negative, this is needed to prevent problems with overflow diff_sign = Signal(reset_less=True) m.d.comb += diff_sign.eq(self.signed_bits.xor()) @@ -115,10 +110,10 @@ def test_jump_eq(tests=NUM_RAND_TESTS): in2 = rand_bits_mix(32) yield dut.alu.in1.eq(in1) yield dut.alu.in2.eq(in2) - yield from eval() + yield Settle() assert (yield dut.jump.cond_true) == (in1 == in2), f"jump_eq failed: in1={hex(in1)}, in2={hex(in2)}, cond_true={(yield dut.jump.cond_true)}" - sim(dut, proc) + sim(dut, proc, sync=False) # test jump if not equal def test_jump_ne(tests=NUM_RAND_TESTS): @@ -132,10 +127,10 @@ def test_jump_ne(tests=NUM_RAND_TESTS): in2 = rand_bits_mix(32) yield dut.alu.in1.eq(in1) yield dut.alu.in2.eq(in2) - yield from eval() + yield Settle() assert (yield dut.jump.cond_true) == (in1 != in2), f"jump_ne failed: in1={hex(in1)}, in2={hex(in2)}, cond_true={(yield dut.jump.cond_true)}" - sim(dut, proc) + sim(dut, proc, sync=False) # test jump if less than unsigned def test_jump_lt_u(tests=NUM_RAND_TESTS): @@ -149,10 +144,10 @@ def test_jump_lt_u(tests=NUM_RAND_TESTS): in2 = rand_bits_mix(32, sus='u') yield dut.alu.in1.eq(in1) yield dut.alu.in2.eq(in2) - yield from eval() + yield Settle() assert (yield dut.jump.cond_true) == (in1 < in2), f"jump_lt_u failed: in1={hex(in1)}, in2={hex(in2)}, cond_true={(yield dut.jump.cond_true)}" - sim(dut, proc) + sim(dut, proc, sync=False) # test jump if less than or equal to unsigned def test_jump_lte_u(tests=NUM_RAND_TESTS): @@ -166,10 +161,10 @@ def test_jump_lte_u(tests=NUM_RAND_TESTS): in2 = rand_bits_mix(32, sus='u') yield dut.alu.in1.eq(in1) yield dut.alu.in2.eq(in2) - yield from eval() + yield Settle() assert (yield dut.jump.cond_true) == (in1 <= in2), f"jump_lte_u failed: in1={hex(in1)}, in2={hex(in2)}, cond_true={(yield dut.jump.cond_true)}" - sim(dut, proc) + sim(dut, proc, sync=False) # test jump if less than signed def test_jump_lt_s(tests=NUM_RAND_TESTS): @@ -183,10 +178,10 @@ def test_jump_lt_s(tests=NUM_RAND_TESTS): in2 = rand_bits_mix(32, sus='s') yield dut.alu.in1.eq(in1) yield dut.alu.in2.eq(in2) - yield from eval() + yield Settle() assert (yield dut.jump.cond_true) == (in1 < in2), f"jump_lt_s failed: in1={hex(in1)}, in2={hex(in2)}, cond_true={(yield dut.jump.cond_true)}" - sim(dut, proc) + sim(dut, proc, sync=False) # test jump if less than or equal to signed def test_jump_lte_s(tests=NUM_RAND_TESTS): @@ -200,10 +195,10 @@ def test_jump_lte_s(tests=NUM_RAND_TESTS): in2 = rand_bits_mix(32, sus='s') yield dut.alu.in1.eq(in1) yield dut.alu.in2.eq(in2) - yield from eval() + yield Settle() assert (yield dut.jump.cond_true) == (in1 <= in2), f"jump_lte_s failed: in1={hex(in1)}, in2={hex(in2)}, cond_true={(yield dut.jump.cond_true)}" - sim(dut, proc) + sim(dut, proc, sync=False) if __name__ == '__main__': diff --git a/hdl/core/reg.py b/hdl/core/reg.py index bacf3f1..8815961 100644 --- a/hdl/core/reg.py +++ b/hdl/core/reg.py @@ -3,7 +3,7 @@ from amaranth import * from amaranth.sim import Settle from hdl.lib.in_out_buff import InOutBuff -from hdl.utils import * +from hdl.utils import cmd, sim, step from hdl.core.alu import ALUFlags @@ -222,11 +222,13 @@ def test_reg_comb_output(): for i in range(16): yield dut.rs1_addr.eq(i) yield Settle() - assert (yield dut.rs1) == i, f'ERROR reading {dut.reg_arr[i].name} != {i}' + rs1 = yield dut.rs1 + assert rs1 == i, f'ERROR reading {dut.reg_arr[i].name}: expected {i} != {rs1}' for i in range(16): yield dut.rs2_addr.eq(i) yield Settle() - assert (yield dut.rs2) == i, f'ERROR reading {dut.reg_arr[i].name} != {i}' + rs2 = yield dut.rs2 + assert rs2 == i, f'EEROR reading {dut.reg_arr[i].name}: expected {i} != {rs2}' sim(dut, proc) # test writeback with writeback disabled @@ -237,7 +239,7 @@ def test_reg_writeback_dsb(): for i in range(16): yield dut.rd_addr.eq(i) yield dut.rd.eq(i + 1) - yield from step() + yield if (i != dut.ip.idx) and (i != dut.flg.idx): # flag gets update by the alu assert (yield dut.reg_arr[i]) == i, f'ERROR writing to {dut.reg_arr[i].name} != {i}' sim(dut, proc) @@ -253,12 +255,12 @@ def test_reg_writeback_en(): yield dut.rd.eq(i - 1) yield from step() if (i != dut.zx.idx) and (i != dut.ip.idx): - assert (yield dut.reg_arr[i]) == i-1, f'ERROR writing to {dut.reg_arr[i].name} != {i-1}' + val = yield dut.reg_arr[i] + assert val == i-1, f'ERROR writing to {dut.reg_arr[i].name}, expected {i-1} != {val}' elif i == dut.zx.idx: - assert (yield dut.zx) == 0, f'ERROR {dut.zx.name} != 0' + assert (yield dut.zx) == 0, f'ERROR {dut.zx.name}, expected 0 != {dut.zx}' elif i == dut.ip.idx: # ip should be incremented and not written to - print((yield dut.ip)) assert (yield dut.reg_arr[i]) == dut.ip.idx+4, f'ERROR {dut.ip.name} != {dut.ip.idx+4} should not be able to be directly written to' sim(dut, proc) diff --git a/hdl/lib/shift_reg.py b/hdl/lib/shift_reg.py index 6966a77..3a217de 100644 --- a/hdl/lib/shift_reg.py +++ b/hdl/lib/shift_reg.py @@ -43,13 +43,13 @@ def test_shiftreg_right(): yield from step() yield dut.load.eq(0) yield dut.en.eq(1) - yield Settle() for _ in range(9): + yield reg_val = yield dut.reg assert reg_val == val, f"Incorrect shift ---EXPECTED: {hex(val)} ---GOT: {hex(reg_val)}" val = val >> 1 - yield from step() + sim(dut, proc) def test_shiftreg_left(): @@ -63,17 +63,17 @@ def test_shiftreg_left(): yield from step() yield dut.load.eq(0) yield dut.en.eq(1) - yield Settle() for _ in range(9): + yield reg_val = yield dut.reg assert reg_val == val, f"Incorrect shift ---EXPECTED: {hex(val)} ---GOT: {hex(reg_val)}" val = (val << 1) & 0xff - yield from step() + sim(dut, proc) if __name__ == '__main__': shift_reg = ShiftReg(8) - cmd(shift_reg) \ No newline at end of file + cmd(shift_reg) diff --git a/hdl/utils.py b/hdl/utils.py index 9c0277d..3cd496a 100644 --- a/hdl/utils.py +++ b/hdl/utils.py @@ -57,10 +57,14 @@ def e2s(e: Enum): ''' return ceil(log2(len(e))) -def sim(dut:Elaboratable, proc: Callable): +def sim(dut:Elaboratable, proc: Callable, sync=True): sim = Simulator(dut) - sim.add_clock(1e-6) - sim.add_sync_process(proc) + + if sync: + sim.add_clock(1e-9) + sim.add_sync_process(proc) + else: + sim.add_process(proc) with sim.write_vcd(os.path.join(VCD_DIR, stack()[1].function + '.vcd')): # get name of caller function sim.run() @@ -70,11 +74,12 @@ def step(cycles=1): yield Settle() # settle comb logic before clock yield # clock edge yield Settle() # settle comb logic after clock - yield Delay(5e-7) # used for debugging, change values on neg edge of clock def eval(): + print(DeprecationWarning('eval() is deprecatated and should not be used')) yield Settle() yield Delay(1e-6) + # bits can be integer or Signal def rand_bits(bits, sus=None, low=None, high=None): -- cgit v1.2.3