From 6c02607b0972976da182c2e7b318dd6f9c5baf20 Mon Sep 17 00:00:00 2001 From: jjsuperpower Date: Mon, 15 Aug 2022 15:23:00 -0500 Subject: added template --- hdl/shift_reg.py | 4 ---- hdl/template.py | 36 ++++++++++++++++++++++++++++++++++++ 2 files changed, 36 insertions(+), 4 deletions(-) create mode 100644 hdl/template.py (limited to 'hdl') diff --git a/hdl/shift_reg.py b/hdl/shift_reg.py index dedc56b..40af39b 100644 --- a/hdl/shift_reg.py +++ b/hdl/shift_reg.py @@ -1,8 +1,4 @@ -import sys -from wsgiref.util import shift_path_info from amaranth import * -from amaranth.back import verilog, cxxrtl -from amaranth.cli import main from amaranth.sim import Simulator, Settle, Delay from utils import cmd diff --git a/hdl/template.py b/hdl/template.py new file mode 100644 index 0000000..5df554c --- /dev/null +++ b/hdl/template.py @@ -0,0 +1,36 @@ +from amaranth import * +from amaranth.sim import Simulator, Settle, Delay + +from utils import cmd + +class Template(Elaboratable): + def __init__(self): + ... + + self.ports = [...] + + def elaborate(self, platform): + m = Module() + + ... + + return m + +def test(filename="out.vcd"): + dut = ... + + def proc1(): + ... + + + sim = Simulator(dut) + sim.add_clock(1e-6) + sim.add_sync_process(proc1) + + with sim.write_vcd(filename): + sim.run() + + +if __name__ == '__main__': + shift_reg = Template(8) + cmd(shift_reg, test) \ No newline at end of file -- cgit v1.2.3