From 26169bec7ae7b85d938f5d3c6e969885f2230541 Mon Sep 17 00:00:00 2001
From: jjsuperpower <jjs29356@gmail.com>
Date: Sun, 19 Jun 2022 22:20:25 -0500
Subject: added hdl folder

---
 hdl/testing/.gitignore     |   1 +
 hdl/testing/hello_world.py | 129 +++++++++++++++++++++++++++++++++++++++++++++
 hdl/testing/inc.v          |  39 ++++++++++++++
 hdl/testing/shift_reg.py   |   0
 hdl/testing/tb_inc.v       |  26 +++++++++
 5 files changed, 195 insertions(+)
 create mode 100644 hdl/testing/.gitignore
 create mode 100644 hdl/testing/hello_world.py
 create mode 100644 hdl/testing/inc.v
 create mode 100644 hdl/testing/shift_reg.py
 create mode 100644 hdl/testing/tb_inc.v

(limited to 'hdl/testing')

diff --git a/hdl/testing/.gitignore b/hdl/testing/.gitignore
new file mode 100644
index 0000000..be78124
--- /dev/null
+++ b/hdl/testing/.gitignore
@@ -0,0 +1 @@
+quartus
\ No newline at end of file
diff --git a/hdl/testing/hello_world.py b/hdl/testing/hello_world.py
new file mode 100644
index 0000000..2167856
--- /dev/null
+++ b/hdl/testing/hello_world.py
@@ -0,0 +1,129 @@
+# from myhdl import block, delay, always, now
+
+# @block
+# def HelloWorld():
+
+#     @always(delay(10))
+#     def say_hello():
+#         print("%s Hello World!" % now())
+
+#     return say_hello
+
+
+# inst = HelloWorld()
+# inst.run_sim(30)
+
+########################################################
+
+# from myhdl import block, Signal, delay, always, now
+
+# @block
+# def HelloWorld():
+
+#     clk = Signal(0)
+
+#     @always(delay(10))
+#     def drive_clk():
+#         clk.next = not clk
+
+#     @always(clk.posedge)
+#     def say_hello():
+#         print("%s Hello World!" % now())
+
+#     return drive_clk, say_hello
+
+
+# inst = HelloWorld()
+# inst.run_sim(50)
+
+########################################################
+
+# from myhdl import block, always_comb, Signal
+
+# @block
+# def mux(z, a, b, sel):
+
+#     """ Multiplexer.
+
+#     z -- mux output
+#     a, b -- data inputs
+#     sel -- control input: select a if asserted, otherwise b
+
+#     """
+
+#     @always_comb
+#     def comb():
+#         if sel == 1:
+#             z.next = a
+#         else:
+#             z.next = b
+
+#     return comb
+
+# import random
+# from myhdl import block, instance, Signal, intbv, delay
+
+# random.seed(5)
+# randrange = random.randrange
+
+# @block
+# def test_mux():
+
+#     z, a, b, sel = [Signal(intbv(0)) for i in range(4)]
+
+#     mux_1 = mux(z, a, b, sel)
+
+#     @instance
+#     def stimulus():
+#         print("z a b sel")
+#         for i in range(12):
+#             a.next, b.next, sel.next = randrange(8), randrange(8), randrange(2)
+#             yield delay(10)
+#             print("%s %s %s %s" % (z, a, b, sel))
+
+#     return mux_1, stimulus
+
+# tb = test_mux()
+# tb.run_sim()
+
+
+########################################################
+
+from myhdl import block, always_seq
+
+@block
+def inc(count, enable, clock, reset):
+    """ Incrementer with enable.
+
+    count -- output
+    enable -- control input, increment when 1
+    clock -- clock input
+    reset -- asynchronous reset input
+    """
+    
+    @always_seq(clock.posedge, reset=reset)
+    def seq():
+        if enable:
+            count.next = count + 1
+
+    return seq
+
+from myhdl import Signal, ResetSignal, modbv
+
+def convert_inc(hdl):
+    """Convert inc block to Verilog or VHDL."""
+
+    m = 8
+
+    count = Signal(modbv(0)[m:])
+    enable = Signal(bool(0))
+    clock  = Signal(bool(0))
+    reset = ResetSignal(0, active=0, isasync=True)
+    
+    inc_1 = inc(count, enable, clock, reset)
+
+    inc_1.convert(hdl=hdl)
+
+
+convert_inc(hdl='Verilog')
+convert_inc(hdl='VHDL')
\ No newline at end of file
diff --git a/hdl/testing/inc.v b/hdl/testing/inc.v
new file mode 100644
index 0000000..2f3291b
--- /dev/null
+++ b/hdl/testing/inc.v
@@ -0,0 +1,39 @@
+// File: inc.v
+// Generated by MyHDL 0.11
+// Date: Sun Jun 19 22:02:52 2022
+
+
+`timescale 1ns/10ps
+
+module inc (
+    count,
+    enable,
+    clock,
+    reset
+);
+// Incrementer with enable.
+// 
+// count -- output
+// enable -- control input, increment when 1
+// clock -- clock input
+// reset -- asynchronous reset input
+
+output [7:0] count;
+reg [7:0] count;
+input enable;
+input clock;
+input reset;
+
+
+always @(posedge clock, negedge reset) begin: INC_SEQ
+    if (reset == 0) begin
+        count <= 0;
+    end
+    else begin
+        if (enable) begin
+            count <= (count + 1);
+        end
+    end
+end
+
+endmodule
diff --git a/hdl/testing/shift_reg.py b/hdl/testing/shift_reg.py
new file mode 100644
index 0000000..e69de29
diff --git a/hdl/testing/tb_inc.v b/hdl/testing/tb_inc.v
new file mode 100644
index 0000000..c0cf480
--- /dev/null
+++ b/hdl/testing/tb_inc.v
@@ -0,0 +1,26 @@
+module tb_inc;
+
+wire [7:0] count;
+reg enable;
+reg clock;
+reg reset;
+
+initial begin
+    $from_myhdl(
+        enable,
+        clock,
+        reset
+    );
+    $to_myhdl(
+        count
+    );
+end
+
+inc dut(
+    count,
+    enable,
+    clock,
+    reset
+);
+
+endmodule
-- 
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