From 382b73b0989dc00093f4e5daa67d4386722b19fb Mon Sep 17 00:00:00 2001
From: jjsuperpower <jjs29356@gmail.com>
Date: Thu, 23 Jun 2022 23:04:28 -0500
Subject: basic myhdl setup working

---
 hdl/testing/shift_reg.py | 103 +++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 103 insertions(+)

(limited to 'hdl/testing/shift_reg.py')

diff --git a/hdl/testing/shift_reg.py b/hdl/testing/shift_reg.py
index e69de29..a98fb4c 100644
--- a/hdl/testing/shift_reg.py
+++ b/hdl/testing/shift_reg.py
@@ -0,0 +1,103 @@
+from fileinput import filename
+from myhdl import *
+import os
+
+from sympy import Si
+
+from constants import *
+
+class ShiftReg():
+    def __init__(self):
+        self.class_name = self.__class__.__name__
+
+    # Main code, this is the actual logic
+    @staticmethod
+    @block
+    def logic(reset: Signal, clk: Signal, in0: Signal, out0: Signal, left_rigt: bool = 1, width: int = 8):
+
+        @always_seq(clk.posedge, reset=reset)
+        def shifter():
+            if not left_rigt:
+                out0.next[width:1] = out0[width-1:0]
+                out0.next[0] = in0
+            else:
+                out0.next[width-1:0] = out0[width:1]
+                out0.next[width-1] = in0
+
+        return shifter
+
+
+    @block
+    def tb(self, func):
+        reset = ResetSignal(0, 0, True)
+        clk = Signal(bool(0))
+        in0 = Signal(0)
+        out0 = Signal(modbv(0)[8:])
+
+        dut = getattr(self, str(func))(reset=reset, clk=clk, in0=in0, out0=out0)
+
+        @always(delay(2))
+        def clock_gen():
+            clk.next = not clk
+
+        @instance
+        def monitor():
+            while True:
+                yield clk.posedge
+                yield delay(1)
+                print(bin(out0, 8))
+
+        @instance
+        def stimulus():
+            yield clk.negedge
+            reset.next = 1
+
+            for i in range(9):
+                yield clk.negedge
+                in0.next = 1
+
+            for i in range(9):
+                yield clk.negedge
+                in0.next = 0
+
+            raise StopSimulation
+
+        return dut, clock_gen, monitor, stimulus
+
+    def convert(self):
+        reset = ResetSignal(0, 0, True)
+        clk = Signal(bool(0))
+        in0 = Signal(bool(0))
+        out0 = Signal(modbv(0)[8:])
+
+        inst = self.logic(reset=reset, clk=clk, in0=in0, out0=out0)
+        inst.convert(hdl='Verilog', path=GEN_VERILOG, name=f"{self.class_name}")
+
+
+    # This function links myhdl to icarus verilog sim
+    def _cosim(self, reset: Signal, clk: Signal, in0: Signal, out0: Signal): #these should have the same signals as logic(), 
+
+        iverilog_cmd = IVERILOG + f"-o {SIM_DIR}{self.class_name}.o {GEN_VERILOG}{self.class_name}.v {GEN_VERILOG}tb_{self.class_name}.v"
+        vvp_cmd = VVP + f"{SIM_DIR}{self.class_name}.o"
+
+        signals = locals()
+        signals.pop('self', None)
+        signals.pop('iverilog_cmd', None)
+        signals.pop('vvp_cmd', None)
+
+        os.system(iverilog_cmd)
+        return Cosimulation(vvp_cmd, **signals)
+
+    def sim(self):
+        tb = self.tb('logic')
+        tb.config_sim(trace=True, tracebackup=False, directory=SIM_DIR, filename=f"{self.class_name}_sim")
+        tb.run_sim()
+
+    def cosim(self):
+        tb = self.tb('_cosim')
+        tb.run_sim()
+
+hdl = ShiftReg()
+hdl.sim()
+hdl.convert()
+hdl.cosim()
-- 
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