From 63626f2f6fc7e8912a349f120e37998cd1a05554 Mon Sep 17 00:00:00 2001 From: jjsuperpower Date: Mon, 5 Sep 2022 20:04:52 -0500 Subject: moveing file around --- hdl/testing/async_reset.py | 21 --------------------- 1 file changed, 21 deletions(-) delete mode 100644 hdl/testing/async_reset.py (limited to 'hdl/testing/async_reset.py') diff --git a/hdl/testing/async_reset.py b/hdl/testing/async_reset.py deleted file mode 100644 index 4760df7..0000000 --- a/hdl/testing/async_reset.py +++ /dev/null @@ -1,21 +0,0 @@ -from amaranth import * -from amaranth.cli import main - - -class ClockDivisor(Elaboratable): - def __init__(self, factor): - self.v = Signal(factor) - self.o = Signal() - - def elaborate(self, platform): - m = Module() - m.d.sync += self.v.eq(self.v + 1) - m.d.comb += self.o.eq(self.v[-1]) - return m - - -if __name__ == "__main__": - m = Module() - m.domains.sync = sync = ClockDomain("sync", async_reset=True) - m.submodules.ctr = ctr = ClockDivisor(factor=16) - main(m, ports=[ctr.o, sync.clk]) \ No newline at end of file -- cgit v1.2.3