From aac788e03219309ae43a0296c773a10a94cfe9f7 Mon Sep 17 00:00:00 2001 From: jjsuperpower Date: Sat, 29 Apr 2023 00:34:07 -0500 Subject: removed unessary delays in tbs --- hdl/lib/shift_reg.py | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'hdl/lib') diff --git a/hdl/lib/shift_reg.py b/hdl/lib/shift_reg.py index 6966a77..3a217de 100644 --- a/hdl/lib/shift_reg.py +++ b/hdl/lib/shift_reg.py @@ -43,13 +43,13 @@ def test_shiftreg_right(): yield from step() yield dut.load.eq(0) yield dut.en.eq(1) - yield Settle() for _ in range(9): + yield reg_val = yield dut.reg assert reg_val == val, f"Incorrect shift ---EXPECTED: {hex(val)} ---GOT: {hex(reg_val)}" val = val >> 1 - yield from step() + sim(dut, proc) def test_shiftreg_left(): @@ -63,17 +63,17 @@ def test_shiftreg_left(): yield from step() yield dut.load.eq(0) yield dut.en.eq(1) - yield Settle() for _ in range(9): + yield reg_val = yield dut.reg assert reg_val == val, f"Incorrect shift ---EXPECTED: {hex(val)} ---GOT: {hex(reg_val)}" val = (val << 1) & 0xff - yield from step() + sim(dut, proc) if __name__ == '__main__': shift_reg = ShiftReg(8) - cmd(shift_reg) \ No newline at end of file + cmd(shift_reg) -- cgit v1.2.3