From 57576da32896277ee6010e314773290faf7ab561 Mon Sep 17 00:00:00 2001 From: jjsuperpower Date: Thu, 13 Oct 2022 21:03:30 -0500 Subject: misc ( I forgot, ok) --- hdl/core/jump_ctl.py | 2 +- hdl/core/reg.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'hdl/core') diff --git a/hdl/core/jump_ctl.py b/hdl/core/jump_ctl.py index 468c2e3..94dd8f2 100644 --- a/hdl/core/jump_ctl.py +++ b/hdl/core/jump_ctl.py @@ -21,7 +21,7 @@ class JumpCtl(Elaboratable): def __init__(self, **kargs): self.alu_flags = Signal(len(ALUFlags), reset_less=True) - self.op = Signal(3, reset_less=True) + self.op = Signal(e2s(JumpOpCodes), reset_less=True) self.signed_bits = Signal(2, reset_less=True) self.cond_true = Signal(reset_less=True) # true if jump condition is met diff --git a/hdl/core/reg.py b/hdl/core/reg.py index 3526408..130de94 100644 --- a/hdl/core/reg.py +++ b/hdl/core/reg.py @@ -89,7 +89,7 @@ class Reg(Elaboratable): self.reg_arr = Array(reg_list) - ports_in = [self.wr_en, self.alu_flgs, self.int_sig, self.iret, self.call, self.jump, self.rd_addr, self.rd, self.rs1_addr, self.rs2_addr] + ports_in = [self.wr_en, self.alu_flgs, self.int_sig, self.iret, self.call, self.jump, self.rd_addr, self.stall, self.rd, self.rs1_addr, self.rs2_addr] ports_out = [self.int_en, self.user_mode, self.rs1, self.rs2, self.ip] self.ports = {'in': ports_in, 'out': ports_out} -- cgit v1.2.3