From d330e0d3da068837684eb51ce1a0e4410440d7a9 Mon Sep 17 00:00:00 2001 From: jjsuperpower Date: Sat, 27 Aug 2022 01:29:54 -0500 Subject: coded but not tested Register file --- doc/ASAP32-ISA.md | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'doc') diff --git a/doc/ASAP32-ISA.md b/doc/ASAP32-ISA.md index c6a0d54..111dec9 100644 --- a/doc/ASAP32-ISA.md +++ b/doc/ASAP32-ISA.md @@ -49,19 +49,18 @@ I propose a different name: EX GP-4 FX GP-5 GX GP-6 - FX GP-7 - FLG Processor Flags + HX GP-7 IP Instruction Pointer SP Stack Pointer + FLG Processor Flags CS0 Control status 0 (saves IP) CS1 Control status 1 (saves SP) CS2 Control status 2 (saves FLG) - RS0 RESERVED + PDA Page Directory Address ### FLG Flag Register Bitfield - These registers are Read/Write - They are automaticaly written to by the CPU - Top-half registers are supervisor only + The lower half is read/write + The upper half can be read or written to in supervisor mode only FLG[0] Carry FLG[1] Overflow @@ -150,10 +149,11 @@ I propose a different name: PUSHR RS SP+=1 ;*SP = RS POPR RS RS = *SP ;SP-=1 PUSHI IMM SP+=1 ;*SP = IMM - INVP IMM Invalidate entry in TLB + INVP IMM Invalidate entry in TLB* JMP IMM Jump to address IMM CALL LABEL CS0=IP; IP=LABEL INT IMM CS0=IP; CS1=SP; CS2=FLG; IP=IDT[IMM]* + SCALL Same as call but is used to make calls to the kernel (fixed IDT address) IRET IP=CS0; SP=CS1; FLG=CS2* RET IP = CS0 SIF Set interrupt flag* -- cgit v1.2.3