From c3fbef6e64506057e832334e1dfa26efde67777e Mon Sep 17 00:00:00 2001 From: jjsuperpower Date: Wed, 10 Aug 2022 22:16:20 -0500 Subject: added make file --- .vscode/configurationCache.log | 2 +- .vscode/dryrun.log | 5 +- .vscode/targets.log | 130 ++++++++++++++++++++++++++++------------- Makefile | 21 +++++++ hdl/shift_reg.py | 84 ++++++++++++++++++++++++++ hdl/testing/async_reset.py | 21 +++++++ hdl/testing/multi_clock.py | 75 ++++++++++++++++++++++++ hdl/testing/shift_reg.py | 100 ------------------------------- hdl/testing/v | 0 hdl/utils.py | 22 +++++++ 10 files changed, 317 insertions(+), 143 deletions(-) create mode 100644 Makefile create mode 100644 hdl/shift_reg.py create mode 100644 hdl/testing/async_reset.py create mode 100644 hdl/testing/multi_clock.py delete mode 100644 hdl/testing/shift_reg.py create mode 100644 hdl/testing/v create mode 100644 hdl/utils.py diff --git a/.vscode/configurationCache.log b/.vscode/configurationCache.log index bab9054..7272748 100644 --- a/.vscode/configurationCache.log +++ b/.vscode/configurationCache.log @@ -1 +1 @@ -{"buildTargets":[],"launchTargets":[],"customConfigurationProvider":{"workspaceBrowse":{"browsePath":[],"compilerArgs":[]},"fileIndex":[]}} \ No newline at end of file +{"buildTargets":["cc","clean","test","test-w"],"launchTargets":[],"customConfigurationProvider":{"workspaceBrowse":{"browsePath":[],"compilerArgs":[]},"fileIndex":[]}} \ No newline at end of file diff --git a/.vscode/dryrun.log b/.vscode/dryrun.log index e3eafb1..3712119 100644 --- a/.vscode/dryrun.log +++ b/.vscode/dryrun.log @@ -1,6 +1,5 @@ -make --dry-run --always-make --keep-going --print-directory +make --dry-run --keep-going --print-directory make: Entering directory '/home/jon/github/ASAP32' +python3 hdl/shift_reg.py cc hdl/shift_reg make: Leaving directory '/home/jon/github/ASAP32' -make: *** No targets specified and no makefile found. Stop. - diff --git a/.vscode/targets.log b/.vscode/targets.log index 5f84ce2..29b4ebe 100644 --- a/.vscode/targets.log +++ b/.vscode/targets.log @@ -1,4 +1,6 @@ make all --print-data-base --no-builtin-variables --no-builtin-rules --question +make: *** No rule to make target 'all'. Stop. + # GNU Make 4.3 # Built for x86_64-suse-linux-gnu # Copyright (C) 1988-2020 Free Software Foundation, Inc. @@ -6,14 +8,18 @@ make all --print-data-base --no-builtin-variables --no-builtin-rules --question # This is free software: you are free to change and redistribute it. # There is NO WARRANTY, to the extent permitted by law. -# Make data base, printed on Thu Aug 4 22:49:23 2022 +# Make data base, printed on Wed Aug 10 22:11:46 2022 # Variables +# environment +PROVIDE_FULLSTACK_ACTION = true # environment JAVA_HOME = /usr/lib64/jvm/java # environment QEMU_AUDIO_DRV = pa +# makefile (from 'Makefile', line 2) +HDL_FOLDER = ./hdl # environment GDK_BACKEND = x11 # environment @@ -23,15 +29,19 @@ NO_AT_BRIDGE = 1 # environment GTK_RC_FILES = /etc/gtk/gtkrc:/home/jon/.gtkrc:/home/jon/.config/gtkrc # environment +UUID = 30e4f429-d9ff-4340-ac46-25a56c8ba58c +# environment WINDOWMANAGER = /usr/bin/startplasma-x11 # environment -VSCODE_CWD = /home/jon/github +VSCODE_CWD = /home/jon # environment GPG_TTY = not a tty # environment MACHTYPE = x86_64-suse-linux # default MAKE_COMMAND := make +# environment +THREE_SCALE_USER_TOKEN = 207c527cfc2a6b8dcf4fa43ad7a976da # automatic @D = $(patsubst %/,%,$(dir $@)) # environment @@ -63,7 +73,7 @@ XDG_DATA_DIRS = /home/jon/.local/share/flatpak/exports/share:/var/lib/flatpak/ex # environment QML_XHR_ALLOW_FILE_READ = 1 # environment -VSCODE_CODE_CACHE_PATH = /home/jon/.config/Code/CachedData/3b889b090b5ad5793f524b5d1d39fda662b96a2a +VSCODE_CODE_CACHE_PATH = /home/jon/.config/Code/CachedData/da76f93349a72022ca4670c1b84860304616aaa2 # environment XDG_SESSION_PATH = /org/freedesktop/DisplayManager/Session0 # environment @@ -73,7 +83,7 @@ SSH_ASKPASS = /usr/libexec/ssh/ssh-askpass # environment LANG = C # environment -XAUTHORITY = /run/user/1000/xauth_jFUnMm +XAUTHORITY = /run/user/1000/xauth_xKCqdm # environment MANPATHISSET = yes # default @@ -87,6 +97,8 @@ MAKEFLAGS = pqrR # makefile CURDIR := /home/jon/github/ASAP32 # environment +UTM_SOURCE = vscode +# environment APPLICATION_INSIGHTS_NO_DIAGNOSTIC_CHANNEL = 1 # environment LESSOPEN = lessopen.sh %s @@ -95,7 +107,7 @@ LESSOPEN = lessopen.sh %s # environment MFLAGS = -pqrR # environment -SSH_AUTH_SOCK = /tmp/ssh-XXXXXX6Sy2Am/agent.1730 +SSH_AUTH_SOCK = /tmp/ssh-XXXXXX5VtrVN/agent.1680 # default .SHELLFLAGS := -c # environment @@ -110,12 +122,12 @@ XCURSOR_THEME = Qogir-dark LESSKEY = /usr/etc/lesskey.bin # environment XDG_SESSION_DESKTOP = KDE -# makefile -MAKEFILE_LIST := +# makefile (from 'Makefile', line 1) +MAKEFILE_LIST := Makefile # automatic @F = $(notdir $@) # environment -VSCODE_PID = 4695 +VSCODE_PID = 20613 # environment XDG_SESSION_TYPE = x11 # environment @@ -127,7 +139,7 @@ INPUT_METHOD = ibus # environment SDK_HOME = /usr/lib64/jvm/java # environment -SESSION_MANAGER = local/WarpDrive:@/tmp/.ICE-unix/2082,unix/WarpDrive:/tmp/.ICE-unix/2082 +SESSION_MANAGER = local/WarpDrive:@/tmp/.ICE-unix/2057,unix/WarpDrive:/tmp/.ICE-unix/2057 # automatic *F = $(notdir $*) # environment @@ -135,7 +147,7 @@ MANPATH = /home/jon/.local/share/man:/usr/local/man:/usr/local/share/man:/usr/sh # environment CHROME_DESKTOP = code-url-handler.desktop # environment -DBUS_SESSION_BUS_ADDRESS = unix:abstract=/tmp/dbus-ymHqyeMEWm,guid=17b1d60c93f024c3f95adad862e5d7e3 +DBUS_SESSION_BUS_ADDRESS = unix:abstract=/tmp/dbus-E50q4J8Dmj,guid=72916cd557b4aa5740f764f362f2a65e # automatic > 1) + + return m + +def test_shift_reg(filename="out.vcd"): + dut = ShiftReg(8) + + def proc1(): + val = 0xAB + + yield dut.load_val.eq(val) + yield dut.en.eq(0) + yield dut.load.eq(1) + yield + yield Settle() + yield dut.load.eq(0) + yield dut.en.eq(1) + + for _ in range(9): + reg_val = yield dut.reg + assert reg_val == val, f"Incorrect shift ---EXPECTED: {hex(val)} ---GOT: {hex(reg_val)}" + val = val >> 1 + yield + yield Settle() + + val = 0xBD + yield dut.load_val.eq(val) + yield dut.load.eq(1) + yield dut.right_left.eq(1) + yield + yield Settle() + yield dut.load.eq(0) + + for _ in range(9): + reg_val = yield dut.reg + assert reg_val == val, f"Incorrect shift ---EXPECTED: {hex(val)} ---GOT: {hex(reg_val)}" + val = (val << 1) & 0xff + yield + yield Settle() + + + + sim = Simulator(dut) + sim.add_clock(1e-6) + sim.add_sync_process(proc1) + + with sim.write_vcd(filename): + sim.run() + + +if __name__ == '__main__': + shift_reg = ShiftReg(8) + cmd(shift_reg, test_shift_reg) \ No newline at end of file diff --git a/hdl/testing/async_reset.py b/hdl/testing/async_reset.py new file mode 100644 index 0000000..4760df7 --- /dev/null +++ b/hdl/testing/async_reset.py @@ -0,0 +1,21 @@ +from amaranth import * +from amaranth.cli import main + + +class ClockDivisor(Elaboratable): + def __init__(self, factor): + self.v = Signal(factor) + self.o = Signal() + + def elaborate(self, platform): + m = Module() + m.d.sync += self.v.eq(self.v + 1) + m.d.comb += self.o.eq(self.v[-1]) + return m + + +if __name__ == "__main__": + m = Module() + m.domains.sync = sync = ClockDomain("sync", async_reset=True) + m.submodules.ctr = ctr = ClockDivisor(factor=16) + main(m, ports=[ctr.o, sync.clk]) \ No newline at end of file diff --git a/hdl/testing/multi_clock.py b/hdl/testing/multi_clock.py new file mode 100644 index 0000000..e377156 --- /dev/null +++ b/hdl/testing/multi_clock.py @@ -0,0 +1,75 @@ +import sys +from amaranth import * +from amaranth.back import verilog, cxxrtl +from amaranth.cli import main +from amaranth.sim import Simulator, Settle, Delay + +BASENAME = "multi_clock" + +class SubM(Elaboratable): + def __init__(self, domain=None): + self.inv = Signal() + self.domain=domain + + def elaborate(self, platform): + m = Module() + + m.d.sync += self.inv.eq(~self.inv) + + return m + +class top(Elaboratable): + def __init__(self): + self.sig_slow = Signal() + self.sig_fast = Signal() + + self.div = Signal(2) + + def elaborate(self, platform): + m = Module() + + m.domains += ClockDomain('slow') + m.d.sync += [self.div.eq(self.div + 1)] + m.d.comb += ClockSignal('slow').eq(self.div[-1]) + + m.submodules.subm1 = SubM() + m.submodules.subm2 = DomainRenamer("slow")(SubM()) + + m.d.sync += self.sig_fast.eq(m.submodules.subm1.inv) + m.d.slow += self.sig_slow.eq(m.submodules.subm2.inv) + + return m + +def test_shift_reg(): + dut = top() + + def proc1(): + for _ in range(16): + yield + yield Settle() + + sim = Simulator(dut) + sim.add_clock(1e-6) + sim.add_sync_process(proc1) + + with sim.write_vcd(BASENAME + '.vcd'): + sim.run() + + +if __name__ == '__main__': + + if sys.argv[1] == "sim": + test_shift_reg() + exit() + + # m = ShiftReg(8) + + # if sys.argv[1] == "v": + # out = verilog.convert(m, ports=m.ports) + # with open(BASENAME + '.v','w') as f: + # f.write(out) + + # elif sys.argv[1] == "cc": + # out = cxxrtl.convert(m, ports=m.ports) + # with open(BASENAME + '.cc','w') as f: + # f.write(out) diff --git a/hdl/testing/shift_reg.py b/hdl/testing/shift_reg.py deleted file mode 100644 index b7c2290..0000000 --- a/hdl/testing/shift_reg.py +++ /dev/null @@ -1,100 +0,0 @@ -import sys -from amaranth import * -from amaranth.back import verilog, cxxrtl -from amaranth.cli import main -from amaranth.sim import Simulator, Settle, Delay - -BASENAME = "shift_reg" - -class ShiftReg(Elaboratable): - def __init__(self, width): - self.load_val = Signal(width, reset=0, reset_less=True) - self.load = Signal() - self.reg = Signal(width) - self.en = Signal() - self.right_left = Signal() - - self.ports = [self.load_val, self.en, self.right_left, self.reg] - - def elaborate(self, platform): - m = Module() - - with m.If(self.load): - m.d.sync += self.reg.eq(self.load_val) - with m.Else(): - with m.If(self.en): - with m.If(self.right_left): - m.d.sync += self.reg.eq(self.reg << 1) - with m.Else(): - m.d.sync += self.reg.eq(self.reg >> 1) - - return m - - -def step(): - yield - yield Settle() - -def test_shift_reg(): - dut = ShiftReg(8) - - def proc1(): - val = 0xAB - - yield dut.load_val.eq(val) - yield dut.en.eq(0) - yield dut.load.eq(1) - yield - yield Settle() - yield dut.load.eq(0) - yield dut.en.eq(1) - - for _ in range(9): - reg_val = yield dut.reg - assert reg_val == val, f"Incorrect shift ---EXPECTED: {hex(val)} ---GOT: {hex(reg_val)}" - val = val >> 1 - yield - yield Settle() - - val = 0xBD - yield dut.load_val.eq(val) - yield dut.load.eq(1) - yield dut.right_left.eq(1) - yield - yield Settle() - yield dut.load.eq(0) - - for _ in range(9): - reg_val = yield dut.reg - assert reg_val == val, f"Incorrect shift ---EXPECTED: {hex(val)} ---GOT: {hex(reg_val)}" - val = (val << 1) & 0xff - yield - yield Settle() - - - - sim = Simulator(dut) - sim.add_clock(1e-6) - sim.add_sync_process(proc1) - - with sim.write_vcd(BASENAME + '.vcd'): - sim.run() - - -if __name__ == '__main__': - - if sys.argv[1] == "sim": - test_shift_reg() - exit() - - m = ShiftReg(8) - - if sys.argv[1] == "v": - out = verilog.convert(m, ports=m.ports) - with open(BASENAME + '.v','w') as f: - f.write(out) - - elif sys.argv[1] == "cc": - out = cxxrtl.convert(m, ports=m.ports) - with open(BASENAME + '.cc','w') as f: - f.write(out) diff --git a/hdl/testing/v b/hdl/testing/v new file mode 100644 index 0000000..e69de29 diff --git a/hdl/utils.py b/hdl/utils.py new file mode 100644 index 0000000..6aad95f --- /dev/null +++ b/hdl/utils.py @@ -0,0 +1,22 @@ +import sys +from typing import Callable +from amaranth import Elaboratable +from amaranth.back import verilog, cxxrtl + +def cmd(hdl, tb:Callable): + if len(sys.argv) <= 1: + exit() + + if sys.argv[1] == "sim": + tb(sys.argv[0].replace('.py', '.vcd')) + exit() + + if sys.argv[1] == "v": + out = verilog.convert(hdl, ports=hdl.ports) + with open(sys.argv[0].replace('.py', '.v'), 'w') as f: + f.write(out) + + elif sys.argv[1] == "cc": + out = cxxrtl.convert(hdl, ports=hdl.ports) + with open(sys.argv[0].replace('.py', '.cc'), 'w') as f: + f.write(out) \ No newline at end of file -- cgit v1.2.3