From 987134966d0c3ab9b1a5775c8f01fa707408780b Mon Sep 17 00:00:00 2001 From: jjsuperpower Date: Sun, 26 Jun 2022 09:40:18 -0500 Subject: restructured folder --- .vscode/configurationCache.log | 1 + .vscode/dryrun.log | 6 + .vscode/settings.json | 3 + .vscode/targets.log | 383 +++++++++++++++++++++++++++++++++++++++++ Makefile | 24 --- hdl/testing/.gitignore | 3 - hdl/testing/Makefile | 12 -- hdl/testing/constants.py | 5 - hdl/testing/delme.py | 11 -- hdl/testing/myhdl.vpi | Bin 32216 -> 0 bytes hdl/testing/myhdl_wrap.py | 31 ---- hdl/testing/shift_reg.py | 119 ------------- hdl/testing/top.py | 26 --- hdl_lab/.gitignore | 6 + hdl_lab/Makefile | 13 ++ hdl_lab/constants.py | 5 + hdl_lab/hdl/shift_reg.py | 119 +++++++++++++ hdl_lab/myhdl.vpi | Bin 0 -> 32216 bytes hdl_lab/myhdl_wrap.py | 31 ++++ 19 files changed, 567 insertions(+), 231 deletions(-) create mode 100644 .vscode/configurationCache.log create mode 100644 .vscode/dryrun.log create mode 100644 .vscode/settings.json create mode 100644 .vscode/targets.log delete mode 100644 Makefile delete mode 100644 hdl/testing/.gitignore delete mode 100644 hdl/testing/Makefile delete mode 100644 hdl/testing/constants.py delete mode 100644 hdl/testing/delme.py delete mode 100755 hdl/testing/myhdl.vpi delete mode 100644 hdl/testing/myhdl_wrap.py delete mode 100644 hdl/testing/shift_reg.py delete mode 100644 hdl/testing/top.py create mode 100644 hdl_lab/.gitignore create mode 100644 hdl_lab/Makefile create mode 100644 hdl_lab/constants.py create mode 100644 hdl_lab/hdl/shift_reg.py create mode 100755 hdl_lab/myhdl.vpi create mode 100644 hdl_lab/myhdl_wrap.py diff --git a/.vscode/configurationCache.log b/.vscode/configurationCache.log new file mode 100644 index 0000000..bab9054 --- /dev/null +++ b/.vscode/configurationCache.log @@ -0,0 +1 @@ +{"buildTargets":[],"launchTargets":[],"customConfigurationProvider":{"workspaceBrowse":{"browsePath":[],"compilerArgs":[]},"fileIndex":[]}} \ No newline at end of file diff --git a/.vscode/dryrun.log b/.vscode/dryrun.log new file mode 100644 index 0000000..927972b --- /dev/null +++ b/.vscode/dryrun.log @@ -0,0 +1,6 @@ +make --dry-run --always-make --keep-going --print-directory +make: Entering directory '/home/jon/Downloads/vertex-isa' +make: Leaving directory '/home/jon/Downloads/vertex-isa' + +make: *** No targets specified and no makefile found. Stop. + diff --git a/.vscode/settings.json b/.vscode/settings.json new file mode 100644 index 0000000..65e1ec0 --- /dev/null +++ b/.vscode/settings.json @@ -0,0 +1,3 @@ +{ + "makefile.extensionOutputFolder": "./.vscode" +} \ No newline at end of file diff --git a/.vscode/targets.log b/.vscode/targets.log new file mode 100644 index 0000000..22515f1 --- /dev/null +++ b/.vscode/targets.log @@ -0,0 +1,383 @@ +make all --print-data-base --no-builtin-variables --no-builtin-rules --question +# GNU Make 4.3 +# Built for x86_64-suse-linux-gnu +# Copyright (C) 1988-2020 Free Software Foundation, Inc. +# License GPLv3+: GNU GPL version 3 or later +# This is free software: you are free to change and redistribute it. +# There is NO WARRANTY, to the extent permitted by law. + +# Make data base, printed on Wed Jun 22 09:25:58 2022 + +# Variables + +# environment +JAVA_HOME = /usr/lib64/jvm/java +# environment +QEMU_AUDIO_DRV = pa +# environment +GDK_BACKEND = x11 +# environment +LC_ALL = C +# environment +NO_AT_BRIDGE = 1 +# environment +GTK_RC_FILES = /etc/gtk/gtkrc:/home/jon/.gtkrc:/home/jon/.config/gtkrc +# environment +VSCODE_IPC_HOOK_EXTHOST = /run/user/1000/vscode-ipc-1d294c6c-3d2e-413d-a467-1ad34d3e6ef7.sock +# environment +WINDOWMANAGER = /usr/bin/startplasma-x11 +# environment +VSCODE_CWD = /home/jon +# environment +GPG_TTY = not a tty +# environment +MACHTYPE = x86_64-suse-linux +# default +MAKE_COMMAND := make +# automatic +@D = $(patsubst %/,%,$(dir $@)) +# environment +PYTHONSTARTUP = /etc/pythonstart +# environment +VSCODE_HANDLES_UNCAUGHT_ERRORS = true +# default +.VARIABLES := +# environment +PWD = /home/jon/Downloads/vertex-isa +# environment +HOST = WarpDrive +# automatic +%D = $(patsubst %/,%,$(dir $%)) +# environment +MORE = -sl +# environment +HOSTNAME = WarpDrive +# environment +MAIL = /var/spool/mail/jon +# environment +XNLSPATH = /usr/share/X11/nls +# environment +XDG_DATA_DIRS = /home/jon/.local/share/flatpak/exports/share:/var/lib/flatpak/exports/share:/usr/share +# automatic +^D = $(patsubst %/,%,$(dir $^)) +# environment +VSCODE_LOG_STACK = false +# environment +QML_XHR_ALLOW_FILE_READ = 1 +# automatic +%F = $(notdir $%) +# environment +VSCODE_CODE_CACHE_PATH = /home/jon/.config/Code/CachedData/dfd34e8260c270da74b5c2d86d61aee4b6d56977 +# environment +XDG_SESSION_PATH = /org/freedesktop/DisplayManager/Session0 +# environment +PROFILEREAD = true +# environment +SSH_ASKPASS = /usr/libexec/ssh/ssh-askpass +# environment +LANG = C +# environment +XAUTHORITY = /run/user/1000/xauth_wDskWU +# environment +MANPATHISSET = yes +# default +.LOADED := +# environment +FROM_HEADER = +# default +.INCLUDE_DIRS = /usr/include /usr/local/include /usr/include +# makefile +MAKEFLAGS = pqrR +# makefile +CURDIR := /home/jon/Downloads/vertex-isa +# environment +VSCODE_PIPE_LOGGING = true +# environment +APPLICATION_INSIGHTS_NO_DIAGNOSTIC_CHANNEL = 1 +# environment +LESSOPEN = lessopen.sh %s +# automatic +*D = $(patsubst %/,%,$(dir $*)) +# environment +MFLAGS = -pqrR +# environment +SSH_AUTH_SOCK = /tmp/ssh-XXXXXX3qXqxT/agent.1648 +# default +.SHELLFLAGS := -c +# environment +HISTSIZE = 1000 +# environment +XDG_CONFIG_DIRS = /home/jon/.config/kdedefaults:/etc/xdg:/usr/etc/xdg +# automatic ++D = $(patsubst %/,%,$(dir $+)) +# environment +XCURSOR_THEME = Qogir-dark +# environment +LESSKEY = /usr/etc/lesskey.bin +# environment +XDG_SESSION_DESKTOP = KDE +# makefile +MAKEFILE_LIST := +# automatic +@F = $(notdir $@) +# environment +VSCODE_VERBOSE_LOGGING = true +# environment +VSCODE_PID = 12064 +# environment +XDG_SESSION_TYPE = x11 +# environment +XAUTHLOCALHOSTNAME = WarpDrive +# automatic +?D = $(patsubst %/,%,$(dir $?)) +# environment +INPUT_METHOD = ibus +# environment +SDK_HOME = /usr/lib64/jvm/java +# environment +SESSION_MANAGER = local/WarpDrive:@/tmp/.ICE-unix/2157,unix/WarpDrive:/tmp/.ICE-unix/2157 +# automatic +*F = $(notdir $*) +# environment +MANPATH = /home/jon/.local/share/man:/usr/local/man:/usr/local/share/man:/usr/share/man:/opt/cross/share/man +# environment +CHROME_DESKTOP = code-url-handler.desktop +# environment +DBUS_SESSION_BUS_ADDRESS = unix:abstract=/tmp/dbus-wAQvM73TPv,guid=5b1fa7134ecbc4a9f950969962b28466 +# automatic +> 1) & 0xFF) | (int(in0) << 7), "Not shifting rigth correctly" - - last_val = int(out0) - - @instance - def reset_test(): - yield clk.negedge - reset.next = True - while True: - reset.next = True - yield delay(randint(25, 28)) - - reset.next = False - yield delay(randint(1,4)) - - @instance - def stimulus(): - for i in range(20): - yield clk.negedge - left_right.next = 0 - in0.next = randint(0, 1) - - for i in range(20): - yield clk.negedge - left_right.next = 1 - in0.next = randint(0, 1) - - raise StopSimulation - - - return dut, clock_gen, monitor, stimulus, reset_test - - def export(self): - reset = Signal(False) - clk = Signal(bool(0)) - load = Signal(intbv(0x00)[8:]) - in0 = Signal(bool(0)) - out0 = Signal(modbv(int(load))[8:]) - left_right = Signal(bool(0)) - - self._export(reset=reset, clk=clk, load=load, in0=in0, out0=out0, left_right=left_right) - - -def test_shift_reg_sim(): - hdl = ShiftReg() - hdl.sim() - -def test_shift_reg_cosim(): - hdl = ShiftReg() - hdl.export() - hdl.cosim() diff --git a/hdl/testing/top.py b/hdl/testing/top.py deleted file mode 100644 index 72e14cd..0000000 --- a/hdl/testing/top.py +++ /dev/null @@ -1,26 +0,0 @@ -from myhdl import * -from constants import GEN_VERILOG -from shift_reg import ShiftReg - -logic = ShiftReg.ShiftReg - -@block -def top(clk, reset, in0, out0): - - node = Signal(modbv(0)[8:]) - - sr0 = logic(clk=clk, reset=reset, in0=in0, out0=node) - sr1 = logic(clk=clk, reset=reset, in0=node(7), out0=out0) - - return sr0, sr1 - -def convert(): - reset = ResetSignal(0, 0, True) - clk = Signal(bool(0)) - in0 = Signal(bool(0)) - out0 = Signal(modbv(0)[8:]) - - inst = top(reset=reset, clk=clk, in0=in0, out0=out0) - inst.convert(hdl='Verilog', path=GEN_VERILOG) - -convert() \ No newline at end of file diff --git a/hdl_lab/.gitignore b/hdl_lab/.gitignore new file mode 100644 index 0000000..bae8235 --- /dev/null +++ b/hdl_lab/.gitignore @@ -0,0 +1,6 @@ +quartus +gen_verilog +simulation +.vscode +__pycache__ +.pytest_cache \ No newline at end of file diff --git a/hdl_lab/Makefile b/hdl_lab/Makefile new file mode 100644 index 0000000..c40b1cf --- /dev/null +++ b/hdl_lab/Makefile @@ -0,0 +1,13 @@ + +HDL_FOLDER = ./hdl +HDL = $(wildcard $(HDL_FOLDER)/*.py) + + +test: + py.test --disable-pytest-warnings -v $(HDL) + +test-w: + py.test -v $(HDL) + +clean: + $(RM) -rf simulation/* gen_verilog/* __pycache__/* .pytest_cache/* \ No newline at end of file diff --git a/hdl_lab/constants.py b/hdl_lab/constants.py new file mode 100644 index 0000000..d40d7c1 --- /dev/null +++ b/hdl_lab/constants.py @@ -0,0 +1,5 @@ +SIM_DIR = './simulation/' +GEN_VERILOG = './gen_verilog/' + +IVERILOG = 'iverilog ' +VVP = 'vvp -M ./ -m myhdl ' \ No newline at end of file diff --git a/hdl_lab/hdl/shift_reg.py b/hdl_lab/hdl/shift_reg.py new file mode 100644 index 0000000..28914f1 --- /dev/null +++ b/hdl_lab/hdl/shift_reg.py @@ -0,0 +1,119 @@ +from turtle import width +from myhdl import * +from myhdl_wrap import Myhdl_Wrapper + +import random +from random import randint + +random.seed(63) + +class ShiftReg(Myhdl_Wrapper): + def __init__(self): + super().__init__() + + # Main code, this is the actual logic + @staticmethod + @block + def ShiftReg(reset: Signal, clk: Signal, load: Signal, in0: Signal, out0: Signal, left_right: Signal): + + width = len(out0) + + @instance + def shifter(): + while True: + yield clk.posedge, reset.negedge + + if not reset: + out0.next = load + else: + if not left_right: + out0.next[width:1] = out0[width-1:0] + out0.next[0] = in0 + else: + out0.next[width-1:0] = out0[width:1] + out0.next[width-1] = in0 + + return shifter + + + @block + def tb(self, func): + reset = Signal(False) + clk = Signal(bool(0)) + load = Signal(intbv(0xA5)[8:]) + in0 = Signal(bool(0)) + out0 = Signal(modbv(int(load))[8:]) + left_right = Signal(bool(0)) + + dut = func(reset=reset, clk=clk, load=load, in0=in0, out0=out0, left_right=left_right) + + @always(delay(2)) + def clock_gen(): + clk.next = not clk + + @instance + def monitor(): + last_val = out0 + + while True: + yield clk.posedge, reset.negedge + yield delay(1) + + if reset == False: + assert out0 == load, "Is output is not zero at reset" + + else: + if not left_right: + assert int(out0) == ((last_val << 1) & 0xFF) | int(in0), "Not shifting left correctly" + else: + assert int(out0) == ((last_val >> 1) & 0xFF) | (int(in0) << 7), "Not shifting rigth correctly" + + last_val = int(out0) + + @instance + def reset_test(): + yield clk.negedge + reset.next = True + while True: + reset.next = True + yield delay(randint(25, 28)) + + reset.next = False + yield delay(randint(1,4)) + + @instance + def stimulus(): + for i in range(20): + yield clk.negedge + left_right.next = 0 + in0.next = randint(0, 1) + + for i in range(20): + yield clk.negedge + left_right.next = 1 + in0.next = randint(0, 1) + + raise StopSimulation + + + return dut, clock_gen, monitor, stimulus, reset_test + + def export(self): + reset = Signal(False) + clk = Signal(bool(0)) + load = Signal(intbv(0x00)[8:]) + in0 = Signal(bool(0)) + out0 = Signal(modbv(int(load))[8:]) + left_right = Signal(bool(0)) + + self._export(reset=reset, clk=clk, load=load, in0=in0, out0=out0, left_right=left_right) + + +def test_shift_reg_sim(): + hdl = ShiftReg() + hdl.sim() + +def test_shift_reg_cosim(): + hdl = ShiftReg() + hdl.export() + hdl.cosim() diff --git a/hdl_lab/myhdl.vpi b/hdl_lab/myhdl.vpi new file mode 100755 index 0000000..1b9d393 Binary files /dev/null and b/hdl_lab/myhdl.vpi differ diff --git a/hdl_lab/myhdl_wrap.py b/hdl_lab/myhdl_wrap.py new file mode 100644 index 0000000..2e8fe4e --- /dev/null +++ b/hdl_lab/myhdl_wrap.py @@ -0,0 +1,31 @@ +import os +from myhdl import * +from constants import * + +class Myhdl_Wrapper(): + def __init__(self): + self.class_name = self.__class__.__name__ + + def _export(self, **kargs): + inst = getattr(self, self.class_name)(**kargs) + inst.convert(hdl='Verilog', path=GEN_VERILOG, name=f"{self.class_name}") + + + + # This function links myhdl to icarus verilog sim + def _cosim(self, **kargs): #these should have the same signals as logic(), + + iverilog_cmd = IVERILOG + f"-o {SIM_DIR}{self.class_name}.o {GEN_VERILOG}{self.class_name}.v {GEN_VERILOG}tb_{self.class_name}.v" + vvp_cmd = VVP + f"{SIM_DIR}{self.class_name}.o" + + os.system(iverilog_cmd) + return Cosimulation(vvp_cmd, **kargs) + + def sim(self): + tb = self.tb(getattr(self, self.class_name)) + tb.config_sim(trace=True, tracebackup=False, directory=SIM_DIR, filename=f"{self.class_name}_sim") + tb.run_sim() + + def cosim(self): + tb = self.tb(self._cosim) + tb.run_sim() \ No newline at end of file -- cgit v1.2.3