From 965821b9bcf018173e0a60f49382568724a5b589 Mon Sep 17 00:00:00 2001 From: jjsuperpower Date: Sun, 7 Aug 2022 10:37:24 -0500 Subject: basic shift register working --- .gitignore | 9 +- .vscode/configurationCache.log | 1 + .vscode/dryrun.log | 6 + .vscode/launch.json | 16 ++ .vscode/settings.json | 3 + .vscode/targets.log | 371 +++++++++++++++++++++++++++++++++++++++++ hdl/testing/shift_reg.py | 100 +++++++++++ hdl/testing/up_counter.py | 50 ++++++ hdl/testing/up_counter_tb.py | 30 ++++ requirements.txt | 1 + 10 files changed, 585 insertions(+), 2 deletions(-) create mode 100644 .vscode/configurationCache.log create mode 100644 .vscode/dryrun.log create mode 100644 .vscode/launch.json create mode 100644 .vscode/settings.json create mode 100644 .vscode/targets.log create mode 100644 hdl/testing/shift_reg.py create mode 100644 hdl/testing/up_counter.py create mode 100644 hdl/testing/up_counter_tb.py create mode 100644 requirements.txt diff --git a/.gitignore b/.gitignore index c1e087a..1642c9d 100644 --- a/.gitignore +++ b/.gitignore @@ -1,4 +1,9 @@ *.pdf -.vscode/ -env/ +.venv __pycache__/ +*quartus +*.v +*.vcd +*.cc +*.bak +*.pytest_cache \ No newline at end of file diff --git a/.vscode/configurationCache.log b/.vscode/configurationCache.log new file mode 100644 index 0000000..bab9054 --- /dev/null +++ b/.vscode/configurationCache.log @@ -0,0 +1 @@ +{"buildTargets":[],"launchTargets":[],"customConfigurationProvider":{"workspaceBrowse":{"browsePath":[],"compilerArgs":[]},"fileIndex":[]}} \ No newline at end of file diff --git a/.vscode/dryrun.log b/.vscode/dryrun.log new file mode 100644 index 0000000..e3eafb1 --- /dev/null +++ b/.vscode/dryrun.log @@ -0,0 +1,6 @@ +make --dry-run --always-make --keep-going --print-directory +make: Entering directory '/home/jon/github/ASAP32' +make: Leaving directory '/home/jon/github/ASAP32' + +make: *** No targets specified and no makefile found. Stop. + diff --git a/.vscode/launch.json b/.vscode/launch.json new file mode 100644 index 0000000..306f58e --- /dev/null +++ b/.vscode/launch.json @@ -0,0 +1,16 @@ +{ + // Use IntelliSense to learn about possible attributes. + // Hover to view descriptions of existing attributes. + // For more information, visit: https://go.microsoft.com/fwlink/?linkid=830387 + "version": "0.2.0", + "configurations": [ + { + "name": "Python: Current File", + "type": "python", + "request": "launch", + "program": "${file}", + "console": "integratedTerminal", + "justMyCode": true + } + ] +} \ No newline at end of file diff --git a/.vscode/settings.json b/.vscode/settings.json new file mode 100644 index 0000000..65e1ec0 --- /dev/null +++ b/.vscode/settings.json @@ -0,0 +1,3 @@ +{ + "makefile.extensionOutputFolder": "./.vscode" +} \ No newline at end of file diff --git a/.vscode/targets.log b/.vscode/targets.log new file mode 100644 index 0000000..5f84ce2 --- /dev/null +++ b/.vscode/targets.log @@ -0,0 +1,371 @@ +make all --print-data-base --no-builtin-variables --no-builtin-rules --question +# GNU Make 4.3 +# Built for x86_64-suse-linux-gnu +# Copyright (C) 1988-2020 Free Software Foundation, Inc. +# License GPLv3+: GNU GPL version 3 or later +# This is free software: you are free to change and redistribute it. +# There is NO WARRANTY, to the extent permitted by law. + +# Make data base, printed on Thu Aug 4 22:49:23 2022 + +# Variables + +# environment +JAVA_HOME = /usr/lib64/jvm/java +# environment +QEMU_AUDIO_DRV = pa +# environment +GDK_BACKEND = x11 +# environment +LC_ALL = C +# environment +NO_AT_BRIDGE = 1 +# environment +GTK_RC_FILES = /etc/gtk/gtkrc:/home/jon/.gtkrc:/home/jon/.config/gtkrc +# environment +WINDOWMANAGER = /usr/bin/startplasma-x11 +# environment +VSCODE_CWD = /home/jon/github +# environment +GPG_TTY = not a tty +# environment +MACHTYPE = x86_64-suse-linux +# default +MAKE_COMMAND := make +# automatic +@D = $(patsubst %/,%,$(dir $@)) +# environment +PYTHONSTARTUP = /etc/pythonstart +# environment +VSCODE_HANDLES_UNCAUGHT_ERRORS = true +# default +.VARIABLES := +# environment +PWD = /home/jon/github/ASAP32 +# environment +HOST = WarpDrive +# automatic +%D = $(patsubst %/,%,$(dir $%)) +# environment +MORE = -sl +# environment +HOSTNAME = WarpDrive +# environment +MAIL = /var/spool/mail/jon +# environment +XNLSPATH = /usr/share/X11/nls +# environment +XDG_DATA_DIRS = /home/jon/.local/share/flatpak/exports/share:/var/lib/flatpak/exports/share:/usr/share +# automatic +^D = $(patsubst %/,%,$(dir $^)) +# automatic +%F = $(notdir $%) +# environment +QML_XHR_ALLOW_FILE_READ = 1 +# environment +VSCODE_CODE_CACHE_PATH = /home/jon/.config/Code/CachedData/3b889b090b5ad5793f524b5d1d39fda662b96a2a +# environment +XDG_SESSION_PATH = /org/freedesktop/DisplayManager/Session0 +# environment +PROFILEREAD = true +# environment +SSH_ASKPASS = /usr/libexec/ssh/ssh-askpass +# environment +LANG = C +# environment +XAUTHORITY = /run/user/1000/xauth_jFUnMm +# environment +MANPATHISSET = yes +# default +.LOADED := +# environment +FROM_HEADER = +# default +.INCLUDE_DIRS = /usr/include /usr/local/include /usr/include +# makefile +MAKEFLAGS = pqrR +# makefile +CURDIR := /home/jon/github/ASAP32 +# environment +APPLICATION_INSIGHTS_NO_DIAGNOSTIC_CHANNEL = 1 +# environment +LESSOPEN = lessopen.sh %s +# automatic +*D = $(patsubst %/,%,$(dir $*)) +# environment +MFLAGS = -pqrR +# environment +SSH_AUTH_SOCK = /tmp/ssh-XXXXXX6Sy2Am/agent.1730 +# default +.SHELLFLAGS := -c +# environment +HISTSIZE = 1000 +# environment +XDG_CONFIG_DIRS = /home/jon/.config/kdedefaults:/etc/xdg:/usr/etc/xdg +# automatic ++D = $(patsubst %/,%,$(dir $+)) +# environment +XCURSOR_THEME = Qogir-dark +# environment +LESSKEY = /usr/etc/lesskey.bin +# environment +XDG_SESSION_DESKTOP = KDE +# makefile +MAKEFILE_LIST := +# automatic +@F = $(notdir $@) +# environment +VSCODE_PID = 4695 +# environment +XDG_SESSION_TYPE = x11 +# environment +XAUTHLOCALHOSTNAME = WarpDrive +# automatic +?D = $(patsubst %/,%,$(dir $?)) +# environment +INPUT_METHOD = ibus +# environment +SDK_HOME = /usr/lib64/jvm/java +# environment +SESSION_MANAGER = local/WarpDrive:@/tmp/.ICE-unix/2082,unix/WarpDrive:/tmp/.ICE-unix/2082 +# automatic +*F = $(notdir $*) +# environment +MANPATH = /home/jon/.local/share/man:/usr/local/man:/usr/local/share/man:/usr/share/man:/opt/cross/share/man +# environment +CHROME_DESKTOP = code-url-handler.desktop +# environment +DBUS_SESSION_BUS_ADDRESS = unix:abstract=/tmp/dbus-ymHqyeMEWm,guid=17b1d60c93f024c3f95adad862e5d7e3 +# automatic +> 1) + + return m + + +def step(): + yield + yield Settle() + +def test_shift_reg(): + dut = ShiftReg(8) + + def proc1(): + val = 0xAB + + yield dut.load_val.eq(val) + yield dut.en.eq(0) + yield dut.load.eq(1) + yield + yield Settle() + yield dut.load.eq(0) + yield dut.en.eq(1) + + for _ in range(9): + reg_val = yield dut.reg + assert reg_val == val, f"Incorrect shift ---EXPECTED: {hex(val)} ---GOT: {hex(reg_val)}" + val = val >> 1 + yield + yield Settle() + + val = 0xBD + yield dut.load_val.eq(val) + yield dut.load.eq(1) + yield dut.right_left.eq(1) + yield + yield Settle() + yield dut.load.eq(0) + + for _ in range(9): + reg_val = yield dut.reg + assert reg_val == val, f"Incorrect shift ---EXPECTED: {hex(val)} ---GOT: {hex(reg_val)}" + val = (val << 1) & 0xff + yield + yield Settle() + + + + sim = Simulator(dut) + sim.add_clock(1e-6) + sim.add_sync_process(proc1) + + with sim.write_vcd(BASENAME + '.vcd'): + sim.run() + + +if __name__ == '__main__': + + if sys.argv[1] == "sim": + test_shift_reg() + exit() + + m = ShiftReg(8) + + if sys.argv[1] == "v": + out = verilog.convert(m, ports=m.ports) + with open(BASENAME + '.v','w') as f: + f.write(out) + + elif sys.argv[1] == "cc": + out = cxxrtl.convert(m, ports=m.ports) + with open(BASENAME + '.cc','w') as f: + f.write(out) diff --git a/hdl/testing/up_counter.py b/hdl/testing/up_counter.py new file mode 100644 index 0000000..050a6b0 --- /dev/null +++ b/hdl/testing/up_counter.py @@ -0,0 +1,50 @@ +from amaranth import * +from amaranth.back import verilog + + +class UpCounter(Elaboratable): + """ + A 16-bit up counter with a fixed limit. + + Parameters + ---------- + limit : int + The value at which the counter overflows. + + Attributes + ---------- + en : Signal, in + The counter is incremented if ``en`` is asserted, and retains + its value otherwise. + ovf : Signal, out + ``ovf`` is asserted when the counter reaches its limit. + """ + + def __init__(self, limit): + self.limit = limit + + # Ports + self.en = Signal() + self.ovf = Signal() + + # State + self.count = Signal(16) + + def elaborate(self, platform): + m = Module() + + m.d.comb += self.ovf.eq(self.count == self.limit) + + with m.If(self.en): + with m.If(self.ovf): + m.d.sync += self.count.eq(0) + with m.Else(): + m.d.sync += self.count.eq(self.count + 1) + + return m + + def to_v(self): + return verilog.convert(self, ports=[self.en, self.ovf]) + +top = UpCounter(25) +print(top.to_v()) \ No newline at end of file diff --git a/hdl/testing/up_counter_tb.py b/hdl/testing/up_counter_tb.py new file mode 100644 index 0000000..7c2e8d2 --- /dev/null +++ b/hdl/testing/up_counter_tb.py @@ -0,0 +1,30 @@ +from amaranth.sim import Simulator +from up_counter import UpCounter + +dut = UpCounter(25) + + +def bench(): + # Disabled counter should not overflow. + yield dut.en.eq(0) + for _ in range(30): + yield + assert not (yield dut.ovf) + + # Once enabled, the counter should overflow in 25 cycles. + yield dut.en.eq(1) + for _ in range(25): + yield + assert not (yield dut.ovf) + yield + assert (yield dut.ovf) + + # The overflow should clear in one cycle. + yield + assert not (yield dut.ovf) + +sim = Simulator(dut) +sim.add_clock(1e-6) # 1 MHz +sim.add_sync_process(bench) +with sim.write_vcd("up_counter.vcd"): + sim.run() \ No newline at end of file diff --git a/requirements.txt b/requirements.txt new file mode 100644 index 0000000..c920901 --- /dev/null +++ b/requirements.txt @@ -0,0 +1 @@ +amaranth[builtin-yosys] \ No newline at end of file -- cgit v1.2.3