From 95d870b5218c40abc5d14cf8acf196663ee518e0 Mon Sep 17 00:00:00 2001
From: jjsuperpower <jjs29356@gmail.com>
Date: Sun, 22 Jan 2023 23:27:04 -0600
Subject: misc

---
 hdl/core/control.py    |  4 ++--
 hdl/testing/memtest.py | 53 ++++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 55 insertions(+), 2 deletions(-)
 create mode 100644 hdl/testing/memtest.py

diff --git a/hdl/core/control.py b/hdl/core/control.py
index 04efe74..ffea409 100644
--- a/hdl/core/control.py
+++ b/hdl/core/control.py
@@ -5,8 +5,8 @@ from enum import Enum, unique
 from hdl.utils import *
 from hdl.lib.in_out_buff import InOutBuff   # used for timing analysis
 
-from alu import AluOpCodes
-from jump_ctl import JumpOpCodes
+from hdl.core.alu import AluOpCodes
+from hdl.core.jump_ctl import JumpOpCodes
 
 
 class Control(Elaboratable):
diff --git a/hdl/testing/memtest.py b/hdl/testing/memtest.py
new file mode 100644
index 0000000..459450a
--- /dev/null
+++ b/hdl/testing/memtest.py
@@ -0,0 +1,53 @@
+from amaranth import *
+from amaranth.cli import main
+
+from amaranth.back import verilog, cxxrtl, rtlil
+
+from hdl.config import *
+from hdl.utils import *
+
+class RegisterFile(Elaboratable):
+    def __init__(self, sim=True):
+        self.adr   = Signal(12)
+        self.dat_r = Signal(16)
+        self.dat_w = Signal(16)
+        self.we    = Signal()
+        self.mem   = Memory(width=16, depth=2**len(self.adr), no_init=True, simulate=sim)
+
+        self.ports = {'in': [self.adr, self.we], 'out': [self.dat_r]}
+
+    def elaborate(self, platform):
+        m = Module()
+        m.submodules.rdport = rdport = self.mem.read_port()
+        m.submodules.wrport = wrport = self.mem.write_port()
+        m.d.comb += [
+            rdport.addr.eq(self.adr),
+            self.dat_r.eq(rdport.data),
+            wrport.addr.eq(self.adr),
+            wrport.data.eq(self.dat_w),
+            wrport.en.eq(self.we),
+        ]
+        return m
+
+
+def test_mem():
+    dut = RegisterFile(sim=True)
+    def proc():
+        yield from eval()
+        yield dut.adr.eq(0)
+        yield dut.dat_w.eq(27)
+        yield dut.we.eq(1)
+        yield from step()
+        yield dut.we.eq(0)
+        yield from step()
+        data_out = yield dut.dat_r
+        print(f'Data out: {data_out}')
+    sim(dut, proc)
+
+
+if __name__ == "__main__":
+    hdl = RegisterFile()
+    # test_mem()
+    out = verilog.convert(hdl, ports=hdl.ports['in'] + hdl.ports['out'])
+    with open(os.path.join(VERILOG_DIR, os.path.basename("memtest.py".replace('.py', '.v'))), 'w') as f:
+        f.write(out)
\ No newline at end of file
-- 
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