From 937140041c91cd2c80f3f5786b0039119dc10514 Mon Sep 17 00:00:00 2001
From: jjsuperpower <jjs29356@gmail.com>
Date: Sun, 22 Jan 2023 23:27:35 -0600
Subject: moving machine codes to central file

---
 hdl/core/machine_code.csv | 48 +++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 48 insertions(+)
 create mode 100644 hdl/core/machine_code.csv

diff --git a/hdl/core/machine_code.csv b/hdl/core/machine_code.csv
new file mode 100644
index 0000000..1d4c383
--- /dev/null
+++ b/hdl/core/machine_code.csv
@@ -0,0 +1,48 @@
+name,type,opcode,mode,description,notes
+ADD,R,1,u,RD = RS1 + RS2,
+ADDC,R,2,u,RD = RS1 + RS2 + FLG[0],
+SUB,R,3,u,RD = RS1 - RS2,
+SUBC,R,4,u,RD = RS1 - RS2 - FLG[0],
+XOR,R,5,u,RD = RS1 ^ RS2,
+OR,R,6,u,RD = RS1 | RS2,
+AND,R,7,u,RD = RS1 & RS2,
+LSL,R,8,u,RD = RS1 << RS2 (logical),
+LSR,R,9,u,RD = RS1 >> RS2 (logical),
+ASR,R,10,u,RD = RS1 >> RS2,
+MULL,R,11,u,RD = (RS1 * RS2) & 0xFFFFFFFF,
+MULH,R,12,u,RD = (RS1 * RS2) >> 32,
+MULLU,R,13,u,RD = RS1 * RS2 & 0xFFFFFFFF (unsigned),
+MULHU,R,14,u,RD = (RS1 * RS2) >> 32 (unsigned),
+DIV,R,15,u,RD = RS1 / RS2,not implemented yet
+DIVU,R,16,u,RD = RS1 / RS2 (unsigned),not implemented yet
+LDW,R,17,u,RD = MEM[RS1 + offset],
+LDWR,R,18,u,RD = MEM[RS1 + RS2],
+STW,R,19,u,MEM[RS1 + offset] = RS2,
+LDB,R,20,u,RD = MEM[RS1 + offset] & 0xFF,
+LDBR,R,21,u,RD = MEM[RS1 + RS2] & 0xFF,
+STB,R,22,u,MEM[RS1 + offset] = RS2 & 0xFF,
+ADDI,I,64,u,RD = RS + IMM,
+ADDIC,I,65,u,RD = RS + IMM + FLG[0],
+SUBI,I,66,u,RD = RS - IMM,
+SUBIC,I,67,u,RD = RS - IMM - FLG[0],
+XORI,I,68,u,RD = RS ^ IMM,
+ORI,I,69,u,RD = RS | IMM,
+ANDI,I,70,u,RD = RS & IMM,
+LSLI,I,71,u,RD = RS << IMM (logical),
+LSRI,I,72,u,RD = RS >> IMM (logical),
+ASRI,I,73,u,RD = RS >> IMM,
+MULIL,I,74,u,RD = (RS * IMM) & 0xFFFFFFFF,
+MULIH,I,75,u,RD = (RS * IMM) >> 32,
+MULIU,I,76,u,RD = (RS * IMM) & 0xFFFFFFFF  (unsigned),
+MULIUH,I,77,u,RD = (RS * IMM) >> 32 (unsigned),
+DIVI,I,78,u,RD = RS / IMM,not implemented yet
+DIVUI,I,79,u,RD = RS / IMM (unsigned),not implemented yet
+JMP,J,128,u,op depends on machine code,
+JMPI,J,129,u,op depends on machine code,
+NOP,C,0,u,Do nothing -> opcode = ZERO ,
+CALL,C,160,u,CS0=IP; IP=CS0,
+RET,C,161,u,"IP = CS0, this is implemented using jmp or call instruction",
+SCALL,C,162,u,CS0=IP; CS1=SP; CS2=FLG; IP=IDT[6]; SP=CS1; FLG[16]=0; FLG[17]=0;,
+INT,C,192,s,CS0=IP; CS1=SP; CS2=FLG; IP=IDT[IMM]; SP=CS1; FLG[16]=0; FLG[17]=0;,
+IRET,C,193,s,IP=CS0; SP=CS1; FLG=CS2;,
+,,,,,
-- 
cgit v1.2.3