diff options
Diffstat (limited to 'hdl_lab')
| -rw-r--r-- | hdl_lab/.gitignore | 1 | ||||
| -rw-r--r-- | hdl_lab/constants.py | 5 | ||||
| -rw-r--r-- | hdl_lab/hdl/myhdl_wrap.py | 16 | ||||
| -rw-r--r-- | hdl_lab/hdl/reset_sync.py | 16 | ||||
| -rw-r--r-- | hdl_lab/myhdl_wrap.py | 31 |
5 files changed, 26 insertions, 43 deletions
diff --git a/hdl_lab/.gitignore b/hdl_lab/.gitignore index bae8235..3f63f69 100644 --- a/hdl_lab/.gitignore +++ b/hdl_lab/.gitignore @@ -3,4 +3,5 @@ gen_verilog simulation .vscode __pycache__ +**__pycache__ .pytest_cache
\ No newline at end of file diff --git a/hdl_lab/constants.py b/hdl_lab/constants.py deleted file mode 100644 index d40d7c1..0000000 --- a/hdl_lab/constants.py +++ /dev/null @@ -1,5 +0,0 @@ -SIM_DIR = './simulation/' -GEN_VERILOG = './gen_verilog/' - -IVERILOG = 'iverilog ' -VVP = 'vvp -M ./ -m myhdl '
\ No newline at end of file diff --git a/hdl_lab/hdl/myhdl_wrap.py b/hdl_lab/hdl/myhdl_wrap.py index 2e8fe4e..56c8c5b 100644 --- a/hdl_lab/hdl/myhdl_wrap.py +++ b/hdl_lab/hdl/myhdl_wrap.py @@ -9,6 +9,22 @@ class Myhdl_Wrapper(): def _export(self, **kargs): inst = getattr(self, self.class_name)(**kargs) inst.convert(hdl='Verilog', path=GEN_VERILOG, name=f"{self.class_name}") + + test_bench_file = GEN_VERILOG + 'tb_' +self.class_name + '.v' + test_bench_tmp_file = GEN_VERILOG + '~tb_' +self.class_name + '.v' + + # this is needed to generate cosim vcd file + with open(test_bench_file) as f_old, open(test_bench_tmp_file, 'w') as f_new: + lines = f_old.readlines() + for line in lines: + f_new.write(line) + if 'initial begin' in line: + f_new.write('\n') + f_new.write(' // Needed to create vcd file\n') + f_new.write(f' $dumpfile ("{SIM_DIR + self.class_name}_cosim.vcd");\n') + f_new.write(f' $dumpvars(0, tb_{self.class_name});\n') + f_new.write('\n') + os.rename(test_bench_tmp_file, test_bench_file) diff --git a/hdl_lab/hdl/reset_sync.py b/hdl_lab/hdl/reset_sync.py index 3116b9e..04ccdeb 100644 --- a/hdl_lab/hdl/reset_sync.py +++ b/hdl_lab/hdl/reset_sync.py @@ -38,7 +38,7 @@ class ResetSync(Myhdl_Wrapper): def tb(self, func: Callable): async_reset = Signal(False) sync_reset = Signal(False) - clk = Signal(bool(0)) + clk = Signal(False) dut = func(clk=clk, async_reset=async_reset, sync_reset=sync_reset) @@ -62,24 +62,26 @@ class ResetSync(Myhdl_Wrapper): yield clk.posedge, async_reset.negedge if async_reset == True: - assert sync_reset.next == False, 'sync Reset did not wait for second clock positive edge' + yield delay(0) + assert sync_reset == False, 'sync Reset did not wait for second clock positive edge' yield clk.posedge, async_reset.negedge if async_reset == True: - assert sync_reset.next == True, 'sync Reset did not set' + yield delay(0) + assert sync_reset == True, 'sync Reset did not set' @instance def stimulus(): for _ in range(500): - yield delay(randint(1,20)) + yield delay(randint(0,20)) if (now()+2) % 4 == 0: # do not create rising edge of reset and clk at the same time yield(delay(1)) async_reset.next = True - yield delay(randint(1, 20)) + yield delay(randint(0, 20)) async_reset.next = False raise StopSimulation @@ -103,7 +105,7 @@ def test_reset_sync_sim(): def test_reset_sync_cosim(): hdl = ResetSync() hdl.export() - # hdl.cosim() + hdl.cosim() -# test_reset_sync_sim() +test_reset_sync_sim() test_reset_sync_cosim() diff --git a/hdl_lab/myhdl_wrap.py b/hdl_lab/myhdl_wrap.py deleted file mode 100644 index 2e8fe4e..0000000 --- a/hdl_lab/myhdl_wrap.py +++ /dev/null @@ -1,31 +0,0 @@ -import os -from myhdl import * -from constants import * - -class Myhdl_Wrapper(): - def __init__(self): - self.class_name = self.__class__.__name__ - - def _export(self, **kargs): - inst = getattr(self, self.class_name)(**kargs) - inst.convert(hdl='Verilog', path=GEN_VERILOG, name=f"{self.class_name}") - - - - # This function links myhdl to icarus verilog sim - def _cosim(self, **kargs): #these should have the same signals as logic(), - - iverilog_cmd = IVERILOG + f"-o {SIM_DIR}{self.class_name}.o {GEN_VERILOG}{self.class_name}.v {GEN_VERILOG}tb_{self.class_name}.v" - vvp_cmd = VVP + f"{SIM_DIR}{self.class_name}.o" - - os.system(iverilog_cmd) - return Cosimulation(vvp_cmd, **kargs) - - def sim(self): - tb = self.tb(getattr(self, self.class_name)) - tb.config_sim(trace=True, tracebackup=False, directory=SIM_DIR, filename=f"{self.class_name}_sim") - tb.run_sim() - - def cosim(self): - tb = self.tb(self._cosim) - tb.run_sim()
\ No newline at end of file |