1 files changed, 9 insertions, 7 deletions
diff --git a/hdl_lab/hdl/reset_sync.py b/hdl_lab/hdl/reset_sync.py
index 3116b9e..04ccdeb 100644
--- a/hdl_lab/hdl/reset_sync.py
+++ b/hdl_lab/hdl/reset_sync.py
@@ -38,7 +38,7 @@ class ResetSync(Myhdl_Wrapper):
     def tb(self, func: Callable):
         async_reset = Signal(False)
         sync_reset = Signal(False)
-        clk = Signal(bool(0))
+        clk = Signal(False)
 
         dut = func(clk=clk, async_reset=async_reset, sync_reset=sync_reset)
 
@@ -62,24 +62,26 @@ class ResetSync(Myhdl_Wrapper):
 
                 yield clk.posedge, async_reset.negedge
                 if async_reset == True:
-                    assert sync_reset.next == False, 'sync Reset did not wait for second clock positive edge'
+                    yield delay(0)
+                    assert sync_reset == False, 'sync Reset did not wait for second clock positive edge'
 
                     yield clk.posedge, async_reset.negedge
                     if async_reset == True:
-                        assert sync_reset.next == True, 'sync Reset did not set'
+                        yield delay(0)
+                        assert sync_reset == True, 'sync Reset did not set'
 
 
 
         @instance
         def stimulus():
             for _ in range(500):
-                yield delay(randint(1,20))
+                yield delay(randint(0,20))
 
                 if (now()+2) % 4 == 0:  # do not create rising edge of reset and clk at the same time
                     yield(delay(1))
 
                 async_reset.next = True
-                yield delay(randint(1, 20))
+                yield delay(randint(0, 20))
                 async_reset.next = False
 
             raise StopSimulation
@@ -103,7 +105,7 @@ def test_reset_sync_sim():
 def test_reset_sync_cosim():
     hdl = ResetSync()
     hdl.export()
-    # hdl.cosim()
+    hdl.cosim()
 
-# test_reset_sync_sim()
+test_reset_sync_sim()
 test_reset_sync_cosim()