diff options
Diffstat (limited to 'hdl')
| -rw-r--r-- | hdl/core/reg.py | 39 |
1 files changed, 28 insertions, 11 deletions
diff --git a/hdl/core/reg.py b/hdl/core/reg.py index df7e948..0fee155 100644 --- a/hdl/core/reg.py +++ b/hdl/core/reg.py @@ -1,9 +1,25 @@ +from enum import unique, Enum from amaranth import * from amaranth.sim import Settle from hdl.lib.in_out_buff import InOutBuff from hdl.utils import cmd, step, sim +from hdl.core.alu import ALUFlags, ALU + + +@unique +class RegFLG(Enum): + carry = ALUFlags.carry.value + zero = ALUFlags.zero.value + negative = ALUFlags.negative.value + overflow = ALUFlags.overflow.value + int_en = 16 + user_mode = 17 + page_en = 18 + halt = 31 # halt/pause the processor, depends on if interupts are enabled + + class Reg(Elaboratable): def __init__(self, **kargs): # sim is only for modularity, does nothing for this @@ -16,7 +32,7 @@ class Reg(Elaboratable): self.rs1_addr = Signal(4) self.rs2_addr = Signal(4) - self.alu_flgs = Signal(5) # flags from alu + self.alu_flgs = Signal(ALU().alu_flags.width) # flags from alu # these signals should be used one hot only self.int_sig = Signal(1) # unconditional interrupt @@ -56,15 +72,15 @@ class Reg(Elaboratable): self.cs2 = Signal(32) #15 self.pda = Signal(32) #16 - # for sake of modularity, make bit locations easily configurable - setattr(self.flg, 'c', self.flg[0]) - setattr(self.flg, 'ov', self.flg[1]) - setattr(self.flg, 'z', self.flg[2]) - setattr(self.flg, 'n', self.flg[3]) - setattr(self.flg, 'od', self.flg[4]) - setattr(self.flg, 'int', self.flg[16]) - setattr(self.flg, 'user_mode', self.flg[17]) - setattr(self.flg, 'page_en', self.flg[18]) + # this is a shortcut for internal testing, use enum RegFLG if using outside of this module + setattr(self.flg, 'c', self.flg[RegFLG.carry.value]) + setattr(self.flg, 'ov', self.flg[RegFLG.overflow.value]) + setattr(self.flg, 'z', self.flg[RegFLG.zero.value]) + setattr(self.flg, 'n', self.flg[RegFLG.negative.value]) + setattr(self.flg, 'int', self.flg[RegFLG.int_en.value]) + setattr(self.flg, 'user_mode', self.flg[RegFLG.user_mode.value]) + setattr(self.flg, 'page_en', self.flg[RegFLG.page_en.value]) + setattr(self.flg, 'halt', self.flg[RegFLG.halt.value]) reg_list = [self.zx, self.ax, self.bx, self.cx, self.dx, self.ex, self.fx, self.gx, self.hx, self.ip, self.sp, self.flg, self.cs0, self.cs1, self.cs2, self.pda] @@ -310,5 +326,6 @@ def test_reg_flg_write_systemmode(): if __name__ == '__main__': - reg = InOutBuff(Reg()) + # reg = InOutBuff(Reg()) + reg = Reg() cmd(reg)
\ No newline at end of file |