diff options
Diffstat (limited to 'hdl')
| -rw-r--r-- | hdl/core.py | 19 |
1 files changed, 11 insertions, 8 deletions
diff --git a/hdl/core.py b/hdl/core.py index c1e38cc..506de96 100644 --- a/hdl/core.py +++ b/hdl/core.py @@ -23,16 +23,20 @@ class Reg(Elaboratable): self.rs1 = Signal(32) self.rs2 = Signal(32) + #interupt enable output signal + self.int_en = Signal(1) + # alu status signals self.alu_flgs = Signal(5) + # signals stack operation self.stack_instr = Signal(1) self.stack_down_up = Signal(1) ################################################################## - # activated when interupt is triggered - self.interupt = Signal(1) + # this is the singal from the control unit, it not affected by interupt enable + self.int_sig = Signal(1) # return from interrupt special self.iret = Signal(1) # jump signal to jump and link (swap ip and cs0) @@ -45,7 +49,6 @@ class Reg(Elaboratable): # internal signals self._user_mode = Signal(1) - self._interupt = Signal(1) self._sp_write = Signal(1) self.zx = Signal(32) #0 @@ -82,23 +85,23 @@ class Reg(Elaboratable): setattr(reg, 'idx', idx) # set idx attribute to each register self.reg_arr = Array(reg_list) - self.ports = [self.wr_en, self.alu_flgs, self.jump, self.interupt, self.iret, self.stack_instr, self.stack_down_up, self.rd_addr, self.rs1_addr, self.rs2_addr, self.rd, self.rs1, self.rs2, self.ip] + self.ports = [self.wr_en, self.alu_flgs, self.jump, self.int_sig, self.int_en, self.iret, self.stack_instr, self.stack_down_up, self.rd_addr, self.rs1_addr, self.rs2_addr, self.rd, self.rs1, self.rs2, self.ip] def elaborate(self, platform=None): m = Module() # user mode override - m.d.comb += self._interupt.eq(self.flg.int & self.interupt) # if the sw guy don't want to be interupted, don't - m.d.comb += self._user_mode.eq(self.flg.user_mode & ~self._interupt) + m.d.comb += self.int_en.eq(self.flg.int) + m.d.comb += self._user_mode.eq(self.flg.user_mode & ~self.int_sig) # toggle ip and cs0 - with m.If(self.jump | self._interupt | self.iret): + with m.If(self.jump | self.int_sig | self.iret): m.d.sync += self.cs0.eq(self.ip) m.d.sync += self.ip.eq(self.cs0) with m.Else(): m.d.sync += self.ip.eq(self.ip + 1) # increment ip only on normal operation - with m.If(self._interupt): + with m.If(self.int_sig): m.d.sync += self.cs1.eq(self.sp) m.d.sync += self.cs2.eq(self.flg) m.d.sync += self.flg.user_mode.eq(0) # set to system mode or iret cannot be used |