diff options
Diffstat (limited to 'hdl/utils.py')
| -rw-r--r-- | hdl/utils.py | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/hdl/utils.py b/hdl/utils.py index 80dc3ee..b496356 100644 --- a/hdl/utils.py +++ b/hdl/utils.py @@ -26,12 +26,12 @@ def cmd(hdl): if sys.argv[1] == "v": out = verilog.convert(hdl, ports=hdl.ports['in'] + hdl.ports['out']) - with open(os.path.join(VERILOG_DIR, sys.argv[0].replace('.py', '.v')), 'w') as f: + with open(os.path.join(VERILOG_DIR, os.path.basename(sys.argv[0]).replace('.py', '.v')), 'w') as f: f.write(out) elif sys.argv[1] == "cc": out = cxxrtl.convert(hdl, ports=hdl.ports['in'] + hdl.ports['out']) - with open(os.path.join(CXXRTL_DIR, sys.argv[0].replace('.py', '.cc')), 'w') as f: + with open(os.path.join(CXXRTL_DIR, os.path.basename(sys.argv[0]).replace('.py', '.cc')), 'w') as f: f.write(out) @@ -41,7 +41,7 @@ def sim(dut:Elaboratable, proc: Callable): sim.add_clock(1e-6) sim.add_sync_process(proc) - with sim.write_vcd(os.path.join(VCD_DIR, stack()[1].function + '.vcd')): + with sim.write_vcd(os.path.join(VCD_DIR, stack()[1].function + '.vcd')): # get name of caller function sim.run() def step(cycles=1): |