diff options
Diffstat (limited to 'hdl/utils.py')
| -rw-r--r-- | hdl/utils.py | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/hdl/utils.py b/hdl/utils.py index 9c0277d..3cd496a 100644 --- a/hdl/utils.py +++ b/hdl/utils.py @@ -57,10 +57,14 @@ def e2s(e: Enum): ''' return ceil(log2(len(e))) -def sim(dut:Elaboratable, proc: Callable): +def sim(dut:Elaboratable, proc: Callable, sync=True): sim = Simulator(dut) - sim.add_clock(1e-6) - sim.add_sync_process(proc) + + if sync: + sim.add_clock(1e-9) + sim.add_sync_process(proc) + else: + sim.add_process(proc) with sim.write_vcd(os.path.join(VCD_DIR, stack()[1].function + '.vcd')): # get name of caller function sim.run() @@ -70,11 +74,12 @@ def step(cycles=1): yield Settle() # settle comb logic before clock yield # clock edge yield Settle() # settle comb logic after clock - yield Delay(5e-7) # used for debugging, change values on neg edge of clock def eval(): + print(DeprecationWarning('eval() is deprecatated and should not be used')) yield Settle() yield Delay(1e-6) + # bits can be integer or Signal def rand_bits(bits, sus=None, low=None, high=None): |