diff options
Diffstat (limited to 'hdl/testing')
| -rw-r--r-- | hdl/testing/.gitignore | 3 | ||||
| -rw-r--r-- | hdl/testing/Makefile | 12 | ||||
| -rw-r--r-- | hdl/testing/constants.py | 5 | ||||
| -rw-r--r-- | hdl/testing/delme.py | 11 | ||||
| -rwxr-xr-x | hdl/testing/myhdl.vpi | bin | 32216 -> 0 bytes | |||
| -rw-r--r-- | hdl/testing/myhdl_wrap.py | 31 | ||||
| -rw-r--r-- | hdl/testing/shift_reg.py | 119 | ||||
| -rw-r--r-- | hdl/testing/top.py | 26 |
8 files changed, 0 insertions, 207 deletions
diff --git a/hdl/testing/.gitignore b/hdl/testing/.gitignore deleted file mode 100644 index 2ddc4e7..0000000 --- a/hdl/testing/.gitignore +++ /dev/null @@ -1,3 +0,0 @@ -quartus -gen_verilog -simulation
\ No newline at end of file diff --git a/hdl/testing/Makefile b/hdl/testing/Makefile deleted file mode 100644 index 5e6391c..0000000 --- a/hdl/testing/Makefile +++ /dev/null @@ -1,12 +0,0 @@ - -HDL = shift_reg.py - - -test: - py.test --disable-pytest-warnings -v $(HDL) - -test-w: - py.test -v $(HDL) - -clean: - $(RM) -rf simulation/* gen_verilog/* __pycache__/* .pytest_cache/*
\ No newline at end of file diff --git a/hdl/testing/constants.py b/hdl/testing/constants.py deleted file mode 100644 index d40d7c1..0000000 --- a/hdl/testing/constants.py +++ /dev/null @@ -1,5 +0,0 @@ -SIM_DIR = './simulation/' -GEN_VERILOG = './gen_verilog/' - -IVERILOG = 'iverilog ' -VVP = 'vvp -M ./ -m myhdl '
\ No newline at end of file diff --git a/hdl/testing/delme.py b/hdl/testing/delme.py deleted file mode 100644 index 1264357..0000000 --- a/hdl/testing/delme.py +++ /dev/null @@ -1,11 +0,0 @@ -class A(): - def __init__(self): - print(f"Parent Class: {self.__class__}") - -class B(A): - def __init__(self): - super().__init__() - print(f"Child Class: {self.__class__}") - - -b = B()
\ No newline at end of file diff --git a/hdl/testing/myhdl.vpi b/hdl/testing/myhdl.vpi Binary files differdeleted file mode 100755 index 1b9d393..0000000 --- a/hdl/testing/myhdl.vpi +++ /dev/null diff --git a/hdl/testing/myhdl_wrap.py b/hdl/testing/myhdl_wrap.py deleted file mode 100644 index 2e8fe4e..0000000 --- a/hdl/testing/myhdl_wrap.py +++ /dev/null @@ -1,31 +0,0 @@ -import os -from myhdl import * -from constants import * - -class Myhdl_Wrapper(): - def __init__(self): - self.class_name = self.__class__.__name__ - - def _export(self, **kargs): - inst = getattr(self, self.class_name)(**kargs) - inst.convert(hdl='Verilog', path=GEN_VERILOG, name=f"{self.class_name}") - - - - # This function links myhdl to icarus verilog sim - def _cosim(self, **kargs): #these should have the same signals as logic(), - - iverilog_cmd = IVERILOG + f"-o {SIM_DIR}{self.class_name}.o {GEN_VERILOG}{self.class_name}.v {GEN_VERILOG}tb_{self.class_name}.v" - vvp_cmd = VVP + f"{SIM_DIR}{self.class_name}.o" - - os.system(iverilog_cmd) - return Cosimulation(vvp_cmd, **kargs) - - def sim(self): - tb = self.tb(getattr(self, self.class_name)) - tb.config_sim(trace=True, tracebackup=False, directory=SIM_DIR, filename=f"{self.class_name}_sim") - tb.run_sim() - - def cosim(self): - tb = self.tb(self._cosim) - tb.run_sim()
\ No newline at end of file diff --git a/hdl/testing/shift_reg.py b/hdl/testing/shift_reg.py deleted file mode 100644 index 28914f1..0000000 --- a/hdl/testing/shift_reg.py +++ /dev/null @@ -1,119 +0,0 @@ -from turtle import width -from myhdl import * -from myhdl_wrap import Myhdl_Wrapper - -import random -from random import randint - -random.seed(63) - -class ShiftReg(Myhdl_Wrapper): - def __init__(self): - super().__init__() - - # Main code, this is the actual logic - @staticmethod - @block - def ShiftReg(reset: Signal, clk: Signal, load: Signal, in0: Signal, out0: Signal, left_right: Signal): - - width = len(out0) - - @instance - def shifter(): - while True: - yield clk.posedge, reset.negedge - - if not reset: - out0.next = load - else: - if not left_right: - out0.next[width:1] = out0[width-1:0] - out0.next[0] = in0 - else: - out0.next[width-1:0] = out0[width:1] - out0.next[width-1] = in0 - - return shifter - - - @block - def tb(self, func): - reset = Signal(False) - clk = Signal(bool(0)) - load = Signal(intbv(0xA5)[8:]) - in0 = Signal(bool(0)) - out0 = Signal(modbv(int(load))[8:]) - left_right = Signal(bool(0)) - - dut = func(reset=reset, clk=clk, load=load, in0=in0, out0=out0, left_right=left_right) - - @always(delay(2)) - def clock_gen(): - clk.next = not clk - - @instance - def monitor(): - last_val = out0 - - while True: - yield clk.posedge, reset.negedge - yield delay(1) - - if reset == False: - assert out0 == load, "Is output is not zero at reset" - - else: - if not left_right: - assert int(out0) == ((last_val << 1) & 0xFF) | int(in0), "Not shifting left correctly" - else: - assert int(out0) == ((last_val >> 1) & 0xFF) | (int(in0) << 7), "Not shifting rigth correctly" - - last_val = int(out0) - - @instance - def reset_test(): - yield clk.negedge - reset.next = True - while True: - reset.next = True - yield delay(randint(25, 28)) - - reset.next = False - yield delay(randint(1,4)) - - @instance - def stimulus(): - for i in range(20): - yield clk.negedge - left_right.next = 0 - in0.next = randint(0, 1) - - for i in range(20): - yield clk.negedge - left_right.next = 1 - in0.next = randint(0, 1) - - raise StopSimulation - - - return dut, clock_gen, monitor, stimulus, reset_test - - def export(self): - reset = Signal(False) - clk = Signal(bool(0)) - load = Signal(intbv(0x00)[8:]) - in0 = Signal(bool(0)) - out0 = Signal(modbv(int(load))[8:]) - left_right = Signal(bool(0)) - - self._export(reset=reset, clk=clk, load=load, in0=in0, out0=out0, left_right=left_right) - - -def test_shift_reg_sim(): - hdl = ShiftReg() - hdl.sim() - -def test_shift_reg_cosim(): - hdl = ShiftReg() - hdl.export() - hdl.cosim() diff --git a/hdl/testing/top.py b/hdl/testing/top.py deleted file mode 100644 index 72e14cd..0000000 --- a/hdl/testing/top.py +++ /dev/null @@ -1,26 +0,0 @@ -from myhdl import * -from constants import GEN_VERILOG -from shift_reg import ShiftReg - -logic = ShiftReg.ShiftReg - -@block -def top(clk, reset, in0, out0): - - node = Signal(modbv(0)[8:]) - - sr0 = logic(clk=clk, reset=reset, in0=in0, out0=node) - sr1 = logic(clk=clk, reset=reset, in0=node(7), out0=out0) - - return sr0, sr1 - -def convert(): - reset = ResetSignal(0, 0, True) - clk = Signal(bool(0)) - in0 = Signal(bool(0)) - out0 = Signal(modbv(0)[8:]) - - inst = top(reset=reset, clk=clk, in0=in0, out0=out0) - inst.convert(hdl='Verilog', path=GEN_VERILOG) - -convert()
\ No newline at end of file |