5 files changed, 0 insertions, 176 deletions
diff --git a/hdl/testing/async_reset.py b/hdl/testing/async_reset.py
deleted file mode 100644
index 4760df7..0000000
--- a/hdl/testing/async_reset.py
+++ /dev/null
@@ -1,21 +0,0 @@
-from amaranth import *
-from amaranth.cli import main
-
-
-class ClockDivisor(Elaboratable):
-    def __init__(self, factor):
-        self.v = Signal(factor)
-        self.o = Signal()
-
-    def elaborate(self, platform):
-        m = Module()
-        m.d.sync += self.v.eq(self.v + 1)
-        m.d.comb += self.o.eq(self.v[-1])
-        return m
-
-
-if __name__ == "__main__":
-    m = Module()
-    m.domains.sync = sync = ClockDomain("sync", async_reset=True)
-    m.submodules.ctr = ctr = ClockDivisor(factor=16)
-    main(m, ports=[ctr.o, sync.clk])
-\ No newline at end of file
diff --git a/hdl/testing/multi_clock.py b/hdl/testing/multi_clock.py
deleted file mode 100644
index e377156..0000000
--- a/hdl/testing/multi_clock.py
+++ /dev/null
@@ -1,75 +0,0 @@
-import sys
-from amaranth import *
-from amaranth.back import verilog, cxxrtl
-from amaranth.cli import main
-from amaranth.sim import Simulator, Settle, Delay
-
-BASENAME = "multi_clock"
-
-class SubM(Elaboratable):
-    def __init__(self, domain=None):
-        self.inv = Signal()
-        self.domain=domain
-
-    def elaborate(self, platform):
-        m = Module()
-
-        m.d.sync += self.inv.eq(~self.inv)
-
-        return m
-
-class top(Elaboratable):
-    def __init__(self):
-        self.sig_slow = Signal()
-        self.sig_fast = Signal()
-
-        self.div = Signal(2)
-
-    def elaborate(self, platform):
-        m = Module()
-
-        m.domains += ClockDomain('slow')
-        m.d.sync += [self.div.eq(self.div + 1)]
-        m.d.comb += ClockSignal('slow').eq(self.div[-1])
-
-        m.submodules.subm1 = SubM()
-        m.submodules.subm2 = DomainRenamer("slow")(SubM())
-
-        m.d.sync += self.sig_fast.eq(m.submodules.subm1.inv)
-        m.d.slow += self.sig_slow.eq(m.submodules.subm2.inv)
-
-        return m
-
-def test_shift_reg():
-    dut = top()
-
-    def proc1():
-        for _ in range(16):
-            yield
-            yield Settle()
-    
-    sim = Simulator(dut)
-    sim.add_clock(1e-6)
-    sim.add_sync_process(proc1)
-    
-    with sim.write_vcd(BASENAME + '.vcd'):
-        sim.run()
-
-
-if __name__ == '__main__':
-
-    if sys.argv[1] == "sim":
-        test_shift_reg()
-        exit()
-
-    # m = ShiftReg(8)
-
-    # if sys.argv[1] == "v":
-    #     out = verilog.convert(m, ports=m.ports)
-    #     with open(BASENAME + '.v','w') as f:
-    #         f.write(out)
-    
-    # elif sys.argv[1] == "cc":
-    #     out = cxxrtl.convert(m, ports=m.ports)
-    #     with open(BASENAME + '.cc','w') as f:
-    #         f.write(out)
diff --git a/hdl/testing/up_counter.py b/hdl/testing/up_counter.py
deleted file mode 100644
index 050a6b0..0000000
--- a/hdl/testing/up_counter.py
+++ /dev/null
@@ -1,50 +0,0 @@
-from amaranth import *
-from amaranth.back import verilog
-
-
-class UpCounter(Elaboratable):
-    """
-    A 16-bit up counter with a fixed limit.
-
-    Parameters
-    ----------
-    limit : int
-        The value at which the counter overflows.
-
-    Attributes
-    ----------
-    en : Signal, in
-        The counter is incremented if ``en`` is asserted, and retains
-        its value otherwise.
-    ovf : Signal, out
-        ``ovf`` is asserted when the counter reaches its limit.
-    """
-    
-    def __init__(self, limit):
-        self.limit = limit
-
-        # Ports
-        self.en  = Signal()
-        self.ovf = Signal()
-
-        # State
-        self.count = Signal(16)
-
-    def elaborate(self, platform):
-        m = Module()
-
-        m.d.comb += self.ovf.eq(self.count == self.limit)
-
-        with m.If(self.en):
-            with m.If(self.ovf):
-                m.d.sync += self.count.eq(0)
-            with m.Else():
-                m.d.sync += self.count.eq(self.count + 1)
-
-        return m
-
-    def to_v(self):
-        return verilog.convert(self, ports=[self.en, self.ovf])
-
-top = UpCounter(25)
-print(top.to_v())
-\ No newline at end of file
diff --git a/hdl/testing/up_counter_tb.py b/hdl/testing/up_counter_tb.py
deleted file mode 100644
index 7c2e8d2..0000000
--- a/hdl/testing/up_counter_tb.py
+++ /dev/null
@@ -1,30 +0,0 @@
-from amaranth.sim import Simulator
-from up_counter import UpCounter
-
-dut = UpCounter(25)
-
-
-def bench():
-    # Disabled counter should not overflow.
-    yield dut.en.eq(0)
-    for _ in range(30):
-        yield
-        assert not (yield dut.ovf)
-
-    # Once enabled, the counter should overflow in 25 cycles.
-    yield dut.en.eq(1)
-    for _ in range(25):
-        yield
-        assert not (yield dut.ovf)
-    yield
-    assert (yield dut.ovf)
-
-    # The overflow should clear in one cycle.
-    yield
-    assert not (yield dut.ovf)
-
-sim = Simulator(dut)
-sim.add_clock(1e-6) # 1 MHz
-sim.add_sync_process(bench)
-with sim.write_vcd("up_counter.vcd"):
-    sim.run()
-\ No newline at end of file
diff --git a/hdl/testing/v b/hdl/testing/v
deleted file mode 100644
index e69de29..0000000
--- a/hdl/testing/v
+++ /dev/null