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-rw-r--r--hdl/testing/up_counter.py50
1 files changed, 50 insertions, 0 deletions
diff --git a/hdl/testing/up_counter.py b/hdl/testing/up_counter.py
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+++ b/hdl/testing/up_counter.py
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+from amaranth import *
+from amaranth.back import verilog
+
+
+class UpCounter(Elaboratable):
+ """
+ A 16-bit up counter with a fixed limit.
+
+ Parameters
+ ----------
+ limit : int
+ The value at which the counter overflows.
+
+ Attributes
+ ----------
+ en : Signal, in
+ The counter is incremented if ``en`` is asserted, and retains
+ its value otherwise.
+ ovf : Signal, out
+ ``ovf`` is asserted when the counter reaches its limit.
+ """
+
+ def __init__(self, limit):
+ self.limit = limit
+
+ # Ports
+ self.en = Signal()
+ self.ovf = Signal()
+
+ # State
+ self.count = Signal(16)
+
+ def elaborate(self, platform):
+ m = Module()
+
+ m.d.comb += self.ovf.eq(self.count == self.limit)
+
+ with m.If(self.en):
+ with m.If(self.ovf):
+ m.d.sync += self.count.eq(0)
+ with m.Else():
+ m.d.sync += self.count.eq(self.count + 1)
+
+ return m
+
+ def to_v(self):
+ return verilog.convert(self, ports=[self.en, self.ovf])
+
+top = UpCounter(25)
+print(top.to_v()) \ No newline at end of file