diff options
Diffstat (limited to 'hdl/testing/simulation/ShiftReg_sim.vcd')
| -rw-r--r-- | hdl/testing/simulation/ShiftReg_sim.vcd | 144 |
1 files changed, 144 insertions, 0 deletions
diff --git a/hdl/testing/simulation/ShiftReg_sim.vcd b/hdl/testing/simulation/ShiftReg_sim.vcd new file mode 100644 index 0000000..f9d6dd4 --- /dev/null +++ b/hdl/testing/simulation/ShiftReg_sim.vcd @@ -0,0 +1,144 @@ +$date + Thu Jun 23 23:03:17 2022 +$end +$version + MyHDL 0.11 +$end +$timescale + 1ns +$end + +$scope module tb $end +$var reg 1 ! clk $end +$var real 1 " in0 $end +$var reg 8 # out0 $end +$var reg 1 $ reset $end +$scope module logic0 $end +$var reg 1 $ reset $end +$var reg 1 ! clk $end +$var real 1 " in0 $end +$var reg 8 # out0 $end +$upscope $end +$upscope $end + +$enddefinitions $end +$dumpvars +0! +s0 " +b00000000 # +0$ +$end +#2 +1! +#3 +#4 +0! +1$ +#6 +1! +#7 +#8 +0! +s1 " +#10 +1! +b10000000 # +#11 +#12 +0! +#14 +1! +b11000000 # +#15 +#16 +0! +#18 +1! +b11100000 # +#19 +#20 +0! +#22 +1! +b11110000 # +#23 +#24 +0! +#26 +1! +b11111000 # +#27 +#28 +0! +#30 +1! +b11111100 # +#31 +#32 +0! +#34 +1! +b11111110 # +#35 +#36 +0! +#38 +1! +b11111111 # +#39 +#40 +0! +#42 +1! +#43 +#44 +0! +s0 " +#46 +1! +b01111111 # +#47 +#48 +0! +#50 +1! +b00111111 # +#51 +#52 +0! +#54 +1! +b00011111 # +#55 +#56 +0! +#58 +1! +b00001111 # +#59 +#60 +0! +#62 +1! +b00000111 # +#63 +#64 +0! +#66 +1! +b00000011 # +#67 +#68 +0! +#70 +1! +b00000001 # +#71 +#72 +0! +#74 +1! +b00000000 # +#75 +#76 +0! |