diff options
Diffstat (limited to 'hdl/testing/shift_reg.py')
| -rw-r--r-- | hdl/testing/shift_reg.py | 26 |
1 files changed, 14 insertions, 12 deletions
diff --git a/hdl/testing/shift_reg.py b/hdl/testing/shift_reg.py index c27b0f7..de2ed3f 100644 --- a/hdl/testing/shift_reg.py +++ b/hdl/testing/shift_reg.py @@ -11,11 +11,13 @@ class ShiftReg(): # Main code, this is the actual logic @staticmethod @block - def ShiftReg(reset: Signal, clk: Signal, in0: Signal, out0: Signal, left_rigt: bool = 0, width: int = 8): + def ShiftReg(reset: Signal, clk: Signal, in0: Signal, out0: Signal, left_right: Signal): + + width = len(out0) @always_seq(clk.posedge, reset=reset) def shifter(): - if not left_rigt: + if not left_right: out0.next[width:1] = out0[width-1:0] out0.next[0] = in0 else: @@ -31,8 +33,9 @@ class ShiftReg(): clk = Signal(bool(0)) in0 = Signal(0) out0 = Signal(modbv(0)[8:]) + left_right = Signal(bool(0)) - dut = getattr(self, str(func))(reset=reset, clk=clk, in0=in0, out0=out0) + dut = getattr(self, str(func))(reset=reset, clk=clk, in0=in0, out0=out0, left_right=left_right) @always(delay(2)) def clock_gen(): @@ -67,27 +70,23 @@ class ShiftReg(): clk = Signal(bool(0)) in0 = Signal(bool(0)) out0 = Signal(modbv(0)[8:]) + left_right = Signal(bool(0)) - inst = self.logic(reset=reset, clk=clk, in0=in0, out0=out0) + inst = self.ShiftReg(reset=reset, clk=clk, in0=in0, out0=out0, left_right=left_right) inst.convert(hdl='Verilog', path=GEN_VERILOG, name=f"{self.class_name}") # This function links myhdl to icarus verilog sim - def _cosim(self, reset: Signal, clk: Signal, in0: Signal, out0: Signal): #these should have the same signals as logic(), + def _cosim(self, **kargs): #these should have the same signals as logic(), iverilog_cmd = IVERILOG + f"-o {SIM_DIR}{self.class_name}.o {GEN_VERILOG}{self.class_name}.v {GEN_VERILOG}tb_{self.class_name}.v" vvp_cmd = VVP + f"{SIM_DIR}{self.class_name}.o" - signals = locals() - signals.pop('self', None) - signals.pop('iverilog_cmd', None) - signals.pop('vvp_cmd', None) - os.system(iverilog_cmd) - return Cosimulation(vvp_cmd, **signals) + return Cosimulation(vvp_cmd, **kargs) def sim(self): - tb = self.tb('logic') + tb = self.tb(self.class_name) tb.config_sim(trace=True, tracebackup=False, directory=SIM_DIR, filename=f"{self.class_name}_sim") tb.run_sim() @@ -101,3 +100,6 @@ def test_shift_reg(): hdl.sim() hdl.convert() hdl.cosim() + + +test_shift_reg()
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