1 files changed, 0 insertions, 75 deletions
diff --git a/hdl/testing/multi_clock.py b/hdl/testing/multi_clock.py
deleted file mode 100644
index e377156..0000000
--- a/hdl/testing/multi_clock.py
+++ /dev/null
@@ -1,75 +0,0 @@
-import sys
-from amaranth import *
-from amaranth.back import verilog, cxxrtl
-from amaranth.cli import main
-from amaranth.sim import Simulator, Settle, Delay
-
-BASENAME = "multi_clock"
-
-class SubM(Elaboratable):
-    def __init__(self, domain=None):
-        self.inv = Signal()
-        self.domain=domain
-
-    def elaborate(self, platform):
-        m = Module()
-
-        m.d.sync += self.inv.eq(~self.inv)
-
-        return m
-
-class top(Elaboratable):
-    def __init__(self):
-        self.sig_slow = Signal()
-        self.sig_fast = Signal()
-
-        self.div = Signal(2)
-
-    def elaborate(self, platform):
-        m = Module()
-
-        m.domains += ClockDomain('slow')
-        m.d.sync += [self.div.eq(self.div + 1)]
-        m.d.comb += ClockSignal('slow').eq(self.div[-1])
-
-        m.submodules.subm1 = SubM()
-        m.submodules.subm2 = DomainRenamer("slow")(SubM())
-
-        m.d.sync += self.sig_fast.eq(m.submodules.subm1.inv)
-        m.d.slow += self.sig_slow.eq(m.submodules.subm2.inv)
-
-        return m
-
-def test_shift_reg():
-    dut = top()
-
-    def proc1():
-        for _ in range(16):
-            yield
-            yield Settle()
-    
-    sim = Simulator(dut)
-    sim.add_clock(1e-6)
-    sim.add_sync_process(proc1)
-    
-    with sim.write_vcd(BASENAME + '.vcd'):
-        sim.run()
-
-
-if __name__ == '__main__':
-
-    if sys.argv[1] == "sim":
-        test_shift_reg()
-        exit()
-
-    # m = ShiftReg(8)
-
-    # if sys.argv[1] == "v":
-    #     out = verilog.convert(m, ports=m.ports)
-    #     with open(BASENAME + '.v','w') as f:
-    #         f.write(out)
-    
-    # elif sys.argv[1] == "cc":
-    #     out = cxxrtl.convert(m, ports=m.ports)
-    #     with open(BASENAME + '.cc','w') as f:
-    #         f.write(out)