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-rw-r--r--hdl/testing/Makefile12
1 files changed, 0 insertions, 12 deletions
diff --git a/hdl/testing/Makefile b/hdl/testing/Makefile
deleted file mode 100644
index 5e6391c..0000000
--- a/hdl/testing/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-
-HDL = shift_reg.py
-
-
-test:
- py.test --disable-pytest-warnings -v $(HDL)
-
-test-w:
- py.test -v $(HDL)
-
-clean:
- $(RM) -rf simulation/* gen_verilog/* __pycache__/* .pytest_cache/* \ No newline at end of file